vlog.prj « xsim « zq_calib_mem « sim_scripts « XUPVVH.ip_user_files « XUPVVH « projects - dram-bender.git - Experimental FPGA-based DRAM memory controller

about summary refs log tree commit diff stats

path: root/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xsim/vlog.prj

blob: d298e2317af9c514e867c7660582847662bda6fb (plain) (blame)

verilog xil_defaultlib  \
"../../../../XUPVVH.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v" \

verilog xil_defaultlib "glbl.v"

nosort