index
:
dram-bender.git
master
Experimental FPGA-based DRAM memory controller
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
projects
/
XUSP3R
/
XUSP3R.srcs
/
sources_1
/
ip
/
phy_ddr4_udimm
Mode
Name
Size
d---------
bd_0
137
log
stats
plain
d---------
ip_0
122
log
stats
plain
d---------
ip_1
100
log
stats
plain
-rw-r--r--
phy_ddr4_udimm.xci
51114
log
stats
plain
blame
-rw-r--r--
phy_ddr4_udimm.xml
433405
log
stats
plain
blame