1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
|
--- XUSP3R.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv
@@ -157,9 +157,13 @@
// used in pushing new write CAS commands into the wrQ shift register. These values are
// calculated for both casslot0 and casslot2.
localparam FABRIC_CASSLOT0 = ( ALL_WR_LATENCY / 4 ) - 2;
+localparam FABRIC_CASSLOT1 = ( ( ALL_WR_LATENCY + 1 ) / 4 ) - 2;
localparam FABRIC_CASSLOT2 = ( ( ALL_WR_LATENCY + 2 ) / 4 ) - 2;
+localparam FABRIC_CASSLOT3 = ( ( ALL_WR_LATENCY + 3 ) / 4 ) - 2;
localparam OFFSET_CASSLOT0 = ( ALL_WR_LATENCY ) % 4;
+localparam OFFSET_CASSLOT1 = ( ALL_WR_LATENCY + 1 ) % 4;
localparam OFFSET_CASSLOT2 = ( ALL_WR_LATENCY + 2 ) % 4;
+localparam OFFSET_CASSLOT3 = ( ALL_WR_LATENCY + 3 ) % 4;
integer i;
@@ -192,10 +196,12 @@
// Output enable shift register fabric load cycle for cal and mc. mccasSlot2 is timing critical.
reg [3:0] oe_0_mux_cal;
wire [3:0] oe_0_mux_cal_nxt = calDone ? FABRIC_CASSLOT0 : FABRIC_CASSLOT2;
-wire [3:0] oe_fabric = mccasSlot2 ? FABRIC_CASSLOT2 : oe_0_mux_cal;
+wire [3:0] oe_fabric = mccasSlot2 ? (casSlot[0] ? FABRIC_CASSLOT3 : FABRIC_CASSLOT2) :
+ (casSlot[0] ? FABRIC_CASSLOT1 : oe_0_mux_cal);
// tCK offset for mc. mccasSlot2 is timing critical.
-wire [1:0] tck_offset = mccasSlot2 ? OFFSET_CASSLOT2 : OFFSET_CASSLOT0;
+wire [1:0] tck_offset = mccasSlot2 ? (casSlot[0] ? OFFSET_CASSLOT3 : OFFSET_CASSLOT2) :
+ (casSlot[0] ? OFFSET_CASSLOT1 : OFFSET_CASSLOT0);
// Output enable shift register load value for cal and mc. mcwrCAS and tck_offset are timing critical.
wire [DBAW+4:0] wrQ_cal_load_value = {winBuf, calRank, OFFSET_CASSLOT2[1:0], 1'b1};
--- XUSP3R.srcs/sources_1/ip/phy_ddr4_x8/rtl/cal/ddr4_v2_2_cal_write.sv
@@ -157,9 +157,13 @@
// used in pushing new write CAS commands into the wrQ shift register. These values are
// calculated for both casslot0 and casslot2.
localparam FABRIC_CASSLOT0 = ( ALL_WR_LATENCY / 4 ) - 2;
+localparam FABRIC_CASSLOT1 = ( ( ALL_WR_LATENCY + 1 ) / 4 ) - 2;
localparam FABRIC_CASSLOT2 = ( ( ALL_WR_LATENCY + 2 ) / 4 ) - 2;
+localparam FABRIC_CASSLOT3 = ( ( ALL_WR_LATENCY + 3 ) / 4 ) - 2;
localparam OFFSET_CASSLOT0 = ( ALL_WR_LATENCY ) % 4;
+localparam OFFSET_CASSLOT1 = ( ALL_WR_LATENCY + 1 ) % 4;
localparam OFFSET_CASSLOT2 = ( ALL_WR_LATENCY + 2 ) % 4;
+localparam OFFSET_CASSLOT3 = ( ALL_WR_LATENCY + 3 ) % 4;
integer i;
@@ -192,10 +196,12 @@
// Output enable shift register fabric load cycle for cal and mc. mccasSlot2 is timing critical.
reg [3:0] oe_0_mux_cal;
wire [3:0] oe_0_mux_cal_nxt = calDone ? FABRIC_CASSLOT0 : FABRIC_CASSLOT2;
-wire [3:0] oe_fabric = mccasSlot2 ? FABRIC_CASSLOT2 : oe_0_mux_cal;
+wire [3:0] oe_fabric = mccasSlot2 ? (casSlot[0] ? FABRIC_CASSLOT3 : FABRIC_CASSLOT2) :
+ (casSlot[0] ? FABRIC_CASSLOT1 : oe_0_mux_cal);
// tCK offset for mc. mccasSlot2 is timing critical.
-wire [1:0] tck_offset = mccasSlot2 ? OFFSET_CASSLOT2 : OFFSET_CASSLOT0;
+wire [1:0] tck_offset = mccasSlot2 ? (casSlot[0] ? OFFSET_CASSLOT3 : OFFSET_CASSLOT2) :
+ (casSlot[0] ? OFFSET_CASSLOT1 : OFFSET_CASSLOT0);
// Output enable shift register load value for cal and mc. mcwrCAS and tck_offset are timing critical.
wire [DBAW+4:0] wrQ_cal_load_value = {winBuf, calRank, OFFSET_CASSLOT2[1:0], 1'b1};
--- XUSP3R.srcs/sources_1/ip/phy_ddr4_x8_1R/rtl/cal/ddr4_v2_2_cal_write.sv
@@ -157,9 +157,13 @@
// used in pushing new write CAS commands into the wrQ shift register. These values are
// calculated for both casslot0 and casslot2.
localparam FABRIC_CASSLOT0 = ( ALL_WR_LATENCY / 4 ) - 2;
+localparam FABRIC_CASSLOT1 = ( ( ALL_WR_LATENCY + 1 ) / 4 ) - 2;
localparam FABRIC_CASSLOT2 = ( ( ALL_WR_LATENCY + 2 ) / 4 ) - 2;
+localparam FABRIC_CASSLOT3 = ( ( ALL_WR_LATENCY + 3 ) / 4 ) - 2;
localparam OFFSET_CASSLOT0 = ( ALL_WR_LATENCY ) % 4;
+localparam OFFSET_CASSLOT1 = ( ALL_WR_LATENCY + 1 ) % 4;
localparam OFFSET_CASSLOT2 = ( ALL_WR_LATENCY + 2 ) % 4;
+localparam OFFSET_CASSLOT3 = ( ALL_WR_LATENCY + 3 ) % 4;
integer i;
@@ -192,10 +196,12 @@
// Output enable shift register fabric load cycle for cal and mc. mccasSlot2 is timing critical.
reg [3:0] oe_0_mux_cal;
wire [3:0] oe_0_mux_cal_nxt = calDone ? FABRIC_CASSLOT0 : FABRIC_CASSLOT2;
-wire [3:0] oe_fabric = mccasSlot2 ? FABRIC_CASSLOT2 : oe_0_mux_cal;
+wire [3:0] oe_fabric = mccasSlot2 ? (casSlot[0] ? FABRIC_CASSLOT3 : FABRIC_CASSLOT2) :
+ (casSlot[0] ? FABRIC_CASSLOT1 : oe_0_mux_cal);
// tCK offset for mc. mccasSlot2 is timing critical.
-wire [1:0] tck_offset = mccasSlot2 ? OFFSET_CASSLOT2 : OFFSET_CASSLOT0;
+wire [1:0] tck_offset = mccasSlot2 ? (casSlot[0] ? OFFSET_CASSLOT3 : OFFSET_CASSLOT2) :
+ (casSlot[0] ? OFFSET_CASSLOT1 : OFFSET_CASSLOT0);
// Output enable shift register load value for cal and mc. mcwrCAS and tck_offset are timing critical.
wire [DBAW+4:0] wrQ_cal_load_value = {winBuf, calRank, OFFSET_CASSLOT2[1:0], 1'b1};
--- XUSP3R.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv
@@ -157,9 +157,13 @@
// used in pushing new write CAS commands into the wrQ shift register. These values are
// calculated for both casslot0 and casslot2.
localparam FABRIC_CASSLOT0 = ( ALL_WR_LATENCY / 4 ) - 2;
+localparam FABRIC_CASSLOT1 = ( ( ALL_WR_LATENCY + 1 ) / 4 ) - 2;
localparam FABRIC_CASSLOT2 = ( ( ALL_WR_LATENCY + 2 ) / 4 ) - 2;
+localparam FABRIC_CASSLOT3 = ( ( ALL_WR_LATENCY + 3 ) / 4 ) - 2;
localparam OFFSET_CASSLOT0 = ( ALL_WR_LATENCY ) % 4;
+localparam OFFSET_CASSLOT1 = ( ALL_WR_LATENCY + 1 ) % 4;
localparam OFFSET_CASSLOT2 = ( ALL_WR_LATENCY + 2 ) % 4;
+localparam OFFSET_CASSLOT3 = ( ALL_WR_LATENCY + 3 ) % 4;
integer i;
@@ -192,10 +196,12 @@
// Output enable shift register fabric load cycle for cal and mc. mccasSlot2 is timing critical.
reg [3:0] oe_0_mux_cal;
wire [3:0] oe_0_mux_cal_nxt = calDone ? FABRIC_CASSLOT0 : FABRIC_CASSLOT2;
-wire [3:0] oe_fabric = mccasSlot2 ? FABRIC_CASSLOT2 : oe_0_mux_cal;
+wire [3:0] oe_fabric = mccasSlot2 ? (casSlot[0] ? FABRIC_CASSLOT3 : FABRIC_CASSLOT2) :
+ (casSlot[0] ? FABRIC_CASSLOT1 : oe_0_mux_cal);
// tCK offset for mc. mccasSlot2 is timing critical.
-wire [1:0] tck_offset = mccasSlot2 ? OFFSET_CASSLOT2 : OFFSET_CASSLOT0;
+wire [1:0] tck_offset = mccasSlot2 ? (casSlot[0] ? OFFSET_CASSLOT3 : OFFSET_CASSLOT2) :
+ (casSlot[0] ? OFFSET_CASSLOT1 : OFFSET_CASSLOT0);
// Output enable shift register load value for cal and mc. mcwrCAS and tck_offset are timing critical.
wire [DBAW+4:0] wrQ_cal_load_value = {winBuf, calRank, OFFSET_CASSLOT2[1:0], 1'b1};
|
