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| author | Leonard Kugis <leonard@kug.is> | 2021-02-11 14:47:52 +0100 |
|---|---|---|
| committer | Leonard Kugis <leonard@kug.is> | 2021-02-11 14:47:52 +0100 |
| commit | 97a74b2f7123e755376ed0cfff0bdaf077a9c3a8 (patch) | |
| tree | 7f7e0cbecd9f8fccce6ce4eac92648dad193aebd | |
| parent | 52f60a20c9d95ecf67b662589d4a4c1160ce0a2a (diff) | |
| download | turboswap-97a74b2f7123e755376ed0cfff0bdaf077a9c3a8.tar.gz | |
Implemented Makefile for convenience
| -rw-r--r-- | Makefile | 83 |
1 files changed, 83 insertions, 0 deletions
diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..f8d94ef --- /dev/null +++ b/Makefile @@ -0,0 +1,83 @@ +# Makefile for TurboSwap FPGA (iCE40UP3K) +# Uses Yosys/IceStorm toolchain + +# FPGA device +DEVICE = iCE40UP3K-SG48 + +# Verilog source files +HDL_SRC = hdl/turbo_top.v \ + hdl/sdio_to_spi.v \ + hdl/spi_controller.v \ + hdl/clock_divider.v \ + hdl/fifo_buffer.v + +# Simulation files +SIM_SRC = sim/tb_turbo_top.v \ + $(HDL_SRC) + +# Build directories +BUILD_DIR = build +SYNTH_DIR = $(BUILD_DIR)/synthesis +PNR_DIR = $(BUILD_DIR)/pnr +BIN_DIR = $(BUILD_DIR)/bin + +# Toolchain executables (adjust paths as needed) +YOSYS = yosys +NEXTPNR = nextpnr-ice40 +ICEPACK = icepack +ICEPROG = iceprog +IVERILOG = iverilog +VVP = vvp + +# Synthesis options +YOSYS_OPTS = -p "synth_ice40 -top turbo_top -json $(SYNTH_DIR)/turbo_top.json" +NEXTPNR_OPTS = --$(DEVICE) --package SG48 --pcf constraints/turbo.pcf --json $(SYNTH_DIR)/turbo_top.json --asc $(PNR_DIR)/turbo_top.asc --freq 25 +ICEPACK_OPTS = + +# Default target +all: $(BIN_DIR)/turbo_top.bin + +# Create directories +dirs: + mkdir -p $(BUILD_DIR) $(SYNTH_DIR) $(PNR_DIR) $(BIN_DIR) + +# Synthesis flow +$(SYNTH_DIR)/turbo_top.json: $(HDL_SRC) | dirs + $(YOSYS) $(YOSYS_OPTS) $(HDL_SRC) + +$(PNR_DIR)/turbo_top.asc: $(SYNTH_DIR)/turbo_top.json constraints/turbo.pcf + $(NEXTPNR) $(NEXTPNR_OPTS) + +$(BIN_DIR)/turbo_top.bin: $(PNR_DIR)/turbo_top.asc + $(ICEPACK) $(ICEPACK_OPTS) $< $@ + +# Programming +program: $(BIN_DIR)/turbo_top.bin + $(ICEPROG) $< + +# Simulation +sim: $(BUILD_DIR)/tb_turbo_top.vvp + $(VVP) $< + +$(BUILD_DIR)/tb_turbo_top.vvp: $(SIM_SRC) + $(IVERILOG) -o $@ $(SIM_SRC) + +# Clean +clean: + rm -rf $(BUILD_DIR) + +distclean: clean + rm -rf *.vcd + +# Help +help: + @echo "TurboSwap FPGA Build System" + @echo "Targets:" + @echo " all - Build bitstream (default)" + @echo " program - Program FPGA" + @echo " sim - Run simulation" + @echo " clean - Clean build artifacts" + @echo " distclean - Clean everything" + @echo " help - Show this help" + +.PHONY: all dirs program sim clean distclean help
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