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authorAtaberk <olgunataberk@gmail.com>2022-09-25 17:22:03 +0200
committerAtaberk <olgunataberk@gmail.com>2022-09-25 17:22:03 +0200
commitdc0b3db1b4f1895a07e5fe280ee3790e87f97b9f (patch)
treeb47203aa281bdd959def4451c84d310cd9cf2e12 /prebuilt/XCU200/XCU200_C1_UDIMM_1R_x8.ltx
downloaddram-bender-dc0b3db1b4f1895a07e5fe280ee3790e87f97b9f.tar.gz
Initial commit
Diffstat (limited to 'prebuilt/XCU200/XCU200_C1_UDIMM_1R_x8.ltx')
-rw-r--r--prebuilt/XCU200/XCU200_C1_UDIMM_1R_x8.ltx32
1 files changed, 32 insertions, 0 deletions
diff --git a/prebuilt/XCU200/XCU200_C1_UDIMM_1R_x8.ltx b/prebuilt/XCU200/XCU200_C1_UDIMM_1R_x8.ltx
new file mode 100644
index 0000000..1366ec4
--- /dev/null
+++ b/prebuilt/XCU200/XCU200_C1_UDIMM_1R_x8.ltx
@@ -0,0 +1,32 @@
+{
+ "ltx_root": {
+ "version": 4,
+ "minor": 0,
+ "ltx_data": [
+ {
+ "name": "EDA_PROBESET",
+ "active": true,
+ "debug_cores": [
+ {
+ "type": "XSDB_V3",
+ "name": "dbg_hub",
+ "spec": "labtools_xsdbm_v3",
+ "clk_input_freq_hz": "41670836"
+ },
+ {
+ "type": "XSDBS_V2",
+ "name": "phy_ddr4_i",
+ "spec": "labtools_xsdbslavelib_v2",
+ "ipName": "DDR4_SDRAM",
+ "core_location": {
+ "user_chain": 1,
+ "slave_index": 0,
+ "bscan_switch_index": 0
+ },
+ "uuid": "A4798F5A1DC8569B9C8CB73395566903"
+ }
+ ]
+ }
+ ]
+ }
+} \ No newline at end of file