diff options
| author | Ataberk <olgunataberk@gmail.com> | 2022-09-25 17:22:03 +0200 |
|---|---|---|
| committer | Ataberk <olgunataberk@gmail.com> | 2022-09-25 17:22:03 +0200 |
| commit | dc0b3db1b4f1895a07e5fe280ee3790e87f97b9f (patch) | |
| tree | b47203aa281bdd959def4451c84d310cd9cf2e12 /prebuilt/XUSP3S/XUSP3S_C2_SODIMM_1R_x8.ltx | |
| download | dram-bender-dc0b3db1b4f1895a07e5fe280ee3790e87f97b9f.tar.gz | |
Initial commit
Diffstat (limited to 'prebuilt/XUSP3S/XUSP3S_C2_SODIMM_1R_x8.ltx')
| -rw-r--r-- | prebuilt/XUSP3S/XUSP3S_C2_SODIMM_1R_x8.ltx | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/prebuilt/XUSP3S/XUSP3S_C2_SODIMM_1R_x8.ltx b/prebuilt/XUSP3S/XUSP3S_C2_SODIMM_1R_x8.ltx new file mode 100644 index 0000000..6e1ee5f --- /dev/null +++ b/prebuilt/XUSP3S/XUSP3S_C2_SODIMM_1R_x8.ltx @@ -0,0 +1,20 @@ +<?xml version="1.0" encoding="UTF-8"?> +<probeData version="2" minor="2"> + <probeset name="EDA_PROBESET" active="true"> + <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT"> + <probeOptions Id="DebugProbeParams"> + <Option Id="BSCAN_SWITCH_INDEX" value="0"/> + <Option Id="CORE_LOCATION" value="1:1"/> + <Option Id="CORE_UUID" value="00000000000000000000000000000000"/> + <Option Id="HUB_CLK_INPUT_FREQ_HZ" value="41666666"/> + <Option Id="HW_ILA" value="u_ila_0"/> + <Option Id="PROBE_PORT" value="0"/> + <Option Id="PROBE_PORT_BITS" value="0"/> + <Option Id="PROBE_PORT_BIT_COUNT" value="1"/> + </probeOptions> + <nets> + <net name="frontend/maint_ctrl/aref_switch_r"/> + </nets> + </probe> + </probeset> +</probeData> |