Initial commit

12 files changed, 1308 insertions, 0 deletions

diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/README.txt
new file mode 100644
index 0000000..67e5cc5
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:23:24 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./phy_ddr4.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './phy_ddr4.sh' script.
+
+./phy_ddr4.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./phy_ddr4.sh -noclean_files
+
+For more information on the script, please type './phy_ddr4.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/compile.do
new file mode 100644
index 0000000..3598ac3
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/compile.do
@@ -0,0 +1,137 @@
+vlib work
+vlib riviera
+
+vlib riviera/xilinx_vip
+vlib riviera/xpm
+vlib riviera/microblaze_v11_0_4
+vlib riviera/xil_defaultlib
+vlib riviera/lib_cdc_v1_0_2
+vlib riviera/proc_sys_reset_v5_0_13
+vlib riviera/lmb_v10_v3_0_11
+vlib riviera/lmb_bram_if_cntlr_v4_0_19
+vlib riviera/blk_mem_gen_v8_4_4
+vlib riviera/iomodule_v3_1_6
+
+vmap xilinx_vip riviera/xilinx_vip
+vmap xpm riviera/xpm
+vmap microblaze_v11_0_4 riviera/microblaze_v11_0_4
+vmap xil_defaultlib riviera/xil_defaultlib
+vmap lib_cdc_v1_0_2 riviera/lib_cdc_v1_0_2
+vmap proc_sys_reset_v5_0_13 riviera/proc_sys_reset_v5_0_13
+vmap lmb_v10_v3_0_11 riviera/lmb_v10_v3_0_11
+vmap lmb_bram_if_cntlr_v4_0_19 riviera/lmb_bram_if_cntlr_v4_0_19
+vmap blk_mem_gen_v8_4_4 riviera/blk_mem_gen_v8_4_4
+vmap iomodule_v3_1_6 riviera/iomodule_v3_1_6
+
+vlog -work xilinx_vip  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm  -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vcom -work microblaze_v11_0_4 -93 \
+"../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd" \
+
+vcom -work lib_cdc_v1_0_2 -93 \
+"../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \
+
+vcom -work proc_sys_reset_v5_0_13 -93 \
+"../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd" \
+
+vcom -work lmb_v10_v3_0_11 -93 \
+"../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd" \
+
+vcom -work lmb_bram_if_cntlr_v4_0_19 -93 \
+"../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/sim/bd_9f2c_ilmb_cntlr_0.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/sim/bd_9f2c_lmb_bram_I_0.v" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/sim/bd_9f2c_second_dlmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/sim/bd_9f2c_second_ilmb_cntlr_0.vhd" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/sim/bd_9f2c_second_lmb_bram_I_0.v" \
+
+vcom -work iomodule_v3_1_6 -93 \
+"../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/sim/bd_9f2c_iomodule_0_0.vhd" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/sim/bd_9f2c.v" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_0/sim/phy_ddr4_microblaze_mcs.v" \
+
+vlog -work xil_defaultlib  -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/custom_parts_ddr4_2016_4_and_above.csv b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/custom_parts_ddr4_2016_4_and_above.csv
new file mode 100755
index 0000000..0e96b29
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/custom_parts_ddr4_2016_4_and_above.csv
@@ -0,0 +1,9 @@
+Part type,Part name,Rank,StackHeight,CA Mirror,Data mask,Address width,Row width,Column width,Bank width,Bank group width,CS width,CKE width,ODT width,CK width,Memory speed grade,Memory density,Component density,Memory device width,Memory component width,Data bits per strobe,IO Voltages,Data widths,Min period,Max period,tCKE,tFAW,tFAW_dlr,tMRD,tRAS,tRCD,tREFI,tRFC,tRFC_dlr,tRP,tRRD_S,tRRD_L,tRRD_dlr,tRTP,tWR,tWTR_S,tWTR_L,tXPR,tZQCS,tZQINIT,tCCD_3ds,cas latency,cas write latency,burst length

+Components,DDR4_CUSTOM,1,1,0,1,17,15,10,2,1,1,1,1,1,107E,4Gb,4Gb,16,16,8,1.2V,"8,16,24,32,40,48,56,64,72,80",1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,13,12,8

+UDIMMs,DDR4_CUSTOM1,2,1,1,1,17,15,10,2,2,2,2,2,2,2G1,8GB,1Gb,72,8,8,1.2V,72,1250,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,12,9,8

+SODIMMs,DDR4_CUSTOM2,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,64,8,8,1.2V,64,1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,14,12,8

+RDIMMs,DDR4_CUSTOM3,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,72,8,8,1.2V,72,938,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,15,11,8

+RDIMMs,DDR4_CUSTOM4,2,2,1,1,17,15,10,2,2,2,2,2,1,83,8GB,4Gb,72,8,8,1.2V,72,833,1600,5000 ps,21000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,100000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,4 tck,16,14,8

+RDIMMs,DDR4_CUSTOM5,2,4,1,0,17,16,10,2,2,2,2,2,1,83,16GB,4Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8

+RDIMMs,64GB,1,1,0,0,18,18,10,2,2,1,1,1,1,83,64GB,16Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8

+LRDIMMs,DDR4_CUSTOM6,4,1,1,0,17,16,10,2,2,4,2,2,2,093E,32GB,8Gb,72,4,4,1.2V,72,938,1600,5000 ps,15000 ps,0,8 tck,33000 ps,14060 ps,7800000 ps,260000 ps,0,14160 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,15,11,8

diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/file_info.txt
new file mode 100644
index 0000000..a852294
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/file_info.txt
@@ -0,0 +1,70 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
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+phy_ddr4_phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
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+ddr4_phy_v2_2_xiphy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_iob_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_iob.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_pll.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_control_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_byte_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
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+phy_ddr4_phy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_infrastructure.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_xsdb_bram.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
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+ddr4_v2_2_cal_wr_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_wr_bit.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_sync.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4.h
new file mode 100755
index 0000000..d82087e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4.h
@@ -0,0 +1,472 @@
+#ifndef IP_PHY_DDR4_H_
+#define IP_PHY_DDR4_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "phy_ddr4_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PHY_DDR4_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4.sh
new file mode 100755
index 0000000..a649ee0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4.sh
@@ -0,0 +1,153 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : phy_ddr4.sh
+# Simulator   : Aldec Riviera-PRO Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:23:24 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: phy_ddr4.sh [-help]
+# usage: phy_ddr4.sh [-lib_map_path]
+# usage: phy_ddr4.sh [-noclean_files]
+# usage: phy_ddr4.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'phy_ddr4.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "phy_ddr4.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/riviera"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: phy_ddr4.sh [-help]\n\
+Usage: phy_ddr4.sh [-lib_map_path]\n\
+Usage: phy_ddr4.sh [-reset_run]\n\
+Usage: phy_ddr4.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4.udo b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4.udo
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4.udo
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4_sc.h
new file mode 100755
index 0000000..036743e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4_sc.h
@@ -0,0 +1,94 @@
+#ifndef IP_PHY_DDR4_SC_H_
+#define IP_PHY_DDR4_SC_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class sim_ddr_v2_0;
+
+class DllExport phy_ddr4_sc : public sc_core::sc_module
+{
+public:
+
+  phy_ddr4_sc(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  sim_ddr_v2_0* mp_impl;
+
+private:
+
+  phy_ddr4_sc(const phy_ddr4_sc&);
+  const phy_ddr4_sc& operator=(const phy_ddr4_sc&);
+
+};
+
+#endif // IP_PHY_DDR4_SC_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/sim_ddr_v2_0.h
new file mode 100755
index 0000000..8dc8c75
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/sim_ddr_v2_0.h
@@ -0,0 +1,221 @@
+// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#include "utils/xtlm_cmnhdr.h"
+#include "xtlm.h"
+#include "report_handler.h"
+#include <sstream>
+#ifdef SDACCEL_WITH_DATA_CONVERTER 
+#include "sdaccel_data_converter.h"
+#endif
+#include "sim_ddrx.h"
+#ifdef TLM2_PROTOCOL_CHEKER
+#include "tlm2_base_protocol_checker.h"
+#endif
+#ifndef sim_ddr_v2_0_H
+#define sim_ddr_v2_0_H
+#include "utils/xsc_stub_port.h"
+#include <utils/xtlm_aximm_passthru_module.h>
+class sim_ddr_v2_0 :public sc_module{
+  public:
+    explicit sim_ddr_v2_0(sc_core::sc_module_name name,
+        xsc::common_cpp::properties model_param_props);
+    ~sim_ddr_v2_0();
+
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket;
+    
+    xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
+    xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
+    SC_HAS_PROCESS(sim_ddr_v2_0);
+
+#ifdef SDACCEL_WITH_DATA_CONVERTER
+    sdaccel_data_converter* sdaccel_data_converter_model;
+#endif
+
+#ifdef TLM2_PROTOCOL_CHEKER        
+    tlm2_base_protocol_checker* checker;
+#endif
+    sc_core::sc_out<bool> c0_ddr4_ui_clk;	
+    sc_core::sc_in<bool> c0_ddr4_aresetn;
+    sc_core::sc_in<bool> sys_rst;
+    sc_core::sc_out< bool > c0_init_calib_complete;
+    sc_core::sc_out< bool > dbg_clk;
+    sc_core::sc_in< bool > c0_sys_clk_p;
+    sc_core::sc_in< bool > c0_sys_clk_n;
+    xsc::utils::xsc_stub_port dbg_bus;
+    xsc::utils::xsc_stub_port c0_ddr4_adr;
+    xsc::utils::xsc_stub_port c0_ddr4_ba;
+    xsc::utils::xsc_stub_port c0_ddr4_cke;
+    xsc::utils::xsc_stub_port c0_ddr4_cs_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dq;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_c;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_t;
+    xsc::utils::xsc_stub_port c0_ddr4_odt;
+    xsc::utils::xsc_stub_port c0_ddr4_bg;
+    xsc::utils::xsc_stub_port c0_ddr4_parity;
+    xsc::utils::xsc_stub_port c0_ddr4_reset_n;
+    xsc::utils::xsc_stub_port c0_ddr4_act_n;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_c;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_t;
+    xsc::utils::xsc_stub_port c0_ddr4_interrupt;
+    xsc::utils::xsc_stub_port addn_ui_clkout1;
+    xsc::utils::xsc_stub_port dbg_rd_data_cmp;
+    xsc::utils::xsc_stub_port dbg_expected_data;
+    xsc::utils::xsc_stub_port dbg_cal_seq;
+    xsc::utils::xsc_stub_port dbg_cal_seq_cnt;
+    xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt;
+    xsc::utils::xsc_stub_port dbg_rd_valid;
+    xsc::utils::xsc_stub_port dbg_cmp_byte;
+    xsc::utils::xsc_stub_port dbg_rd_data;
+    xsc::utils::xsc_stub_port dbg_cplx_config;
+    xsc::utils::xsc_stub_port dbg_cplx_status;
+    xsc::utils::xsc_stub_port dbg_io_address;
+    xsc::utils::xsc_stub_port dbg_pllGate;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp;
+    xsc::utils::xsc_stub_port cal_r0_status;
+    xsc::utils::xsc_stub_port cal_post_status;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete;
+    xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error;
+    xsc::utils::xsc_stub_port c0_ddr4_app_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_cmd;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy;
+    xsc::utils::xsc_stub_port rdDataEn;
+    xsc::utils::xsc_stub_port rdDataEnd;
+    xsc::utils::xsc_stub_port per_rd_done;
+    xsc::utils::xsc_stub_port rmw_rd_done;
+    xsc::utils::xsc_stub_port wrDataEn;
+    xsc::utils::xsc_stub_port mc_ACT_n;
+    xsc::utils::xsc_stub_port mcCasSlot;
+    xsc::utils::xsc_stub_port mcCasSlot2;
+    xsc::utils::xsc_stub_port mcRdCAS;
+    xsc::utils::xsc_stub_port mcWrCAS;
+    xsc::utils::xsc_stub_port winInjTxn;
+    xsc::utils::xsc_stub_port winRmw;
+    xsc::utils::xsc_stub_port gt_data_ready;
+    xsc::utils::xsc_stub_port winRank;
+    xsc::utils::xsc_stub_port tCWL;
+    xsc::utils::xsc_stub_port wrData;
+    xsc::utils::xsc_stub_port wrDataMask;
+    xsc::utils::xsc_stub_port rdData;
+    xsc::utils::xsc_stub_port mc_ADR;
+    xsc::utils::xsc_stub_port mc_BA;
+    xsc::utils::xsc_stub_port mc_CKE;
+    xsc::utils::xsc_stub_port mc_CS_n;
+    xsc::utils::xsc_stub_port mc_ODT;
+    xsc::utils::xsc_stub_port dBufAdr;
+    xsc::utils::xsc_stub_port rdDataAddr;
+    xsc::utils::xsc_stub_port wrDataAddr;
+    xsc::utils::xsc_stub_port winBuf;
+    xsc::utils::xsc_stub_port ddr4_act_n;
+    xsc::utils::xsc_stub_port ddr4_adr;
+    xsc::utils::xsc_stub_port ddr4_ba;
+    xsc::utils::xsc_stub_port ddr4_bg;
+    xsc::utils::xsc_stub_port ddr4_par;
+    xsc::utils::xsc_stub_port ddr4_cke;
+    xsc::utils::xsc_stub_port ddr4_odt;
+    xsc::utils::xsc_stub_port ddr4_cs_n;
+    xsc::utils::xsc_stub_port ddr4_ck_t;
+    xsc::utils::xsc_stub_port ddr4_ck_c;
+    xsc::utils::xsc_stub_port ddr4_reset_n;
+    xsc::utils::xsc_stub_port ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port ddr4_dq;
+    xsc::utils::xsc_stub_port ddr4_dqs_c;
+    xsc::utils::xsc_stub_port ddr4_dqs_t;
+    xsc::utils::xsc_stub_port mc_BG;
+    
+    sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+    sc_core::sc_in< bool > c0_sys_clk_i;
+    sc_core::sc_signal<bool>out1;
+    sc_core::sc_signal<bool>out2;
+    xsc::common_cpp::report_handler* m_report_handler;
+    std::stringstream m_ss;
+    float clk;
+    void generateReset();
+  protected:
+
+  private:
+    xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model;
+
+    std::map<std::string, int> user_param_int;
+    std::map<std::string, std::string> user_param_string;
+
+};
+#endif
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/simulate.do
new file mode 100644
index 0000000..98bfe9c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/simulate.do
@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim +access +r +m+phy_ddr4 -L xilinx_vip -L xpm -L microblaze_v11_0_4 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_11 -L lmb_bram_if_cntlr_v4_0_19 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_6 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.phy_ddr4 xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {phy_ddr4.udo}
+
+run -all
+
+endsim
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR