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| author | Ataberk <olgunataberk@gmail.com> | 2022-09-25 17:22:03 +0200 |
|---|---|---|
| committer | Ataberk <olgunataberk@gmail.com> | 2022-09-25 17:22:03 +0200 |
| commit | dc0b3db1b4f1895a07e5fe280ee3790e87f97b9f (patch) | |
| tree | b47203aa281bdd959def4451c84d310cd9cf2e12 /projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/U200.smi | |
| download | dram-bender-dc0b3db1b4f1895a07e5fe280ee3790e87f97b9f.tar.gz | |
Initial commit
Diffstat (limited to 'projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/U200.smi')
| -rw-r--r-- | projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/U200.smi | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/U200.smi b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/U200.smi new file mode 100644 index 0000000..f20b0a8 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/U200.smi @@ -0,0 +1,30 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2020.2 (64-bit) --> +<!-- SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 --> +<!-- --> +<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. --> +<!-- Nov 18 2020 --> +<!-- --> +<!-- This file is generated by the software with the Tcl write_mem_info command. --> +<!-- Do not edit this file. --> + +<MemInfoSimulation Version="1" Minor="1"> + <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I"> + <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_64K_1_ADDR_SPACE" ECC="NONE" Begin="0" End="98303"> + <BusBlock> + <BitLane MemType="lmb_bram_I_64K_1_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303"> + <DataWidth MSB="31" LSB="0"/> + <AddressRange Begin="0" End="16383"/> + <Parity ON="false" NumBits="0"/> + <MemFile Name="bd_ba6a_lmb_bram_I_0.mem"/> + </BitLane> + </BusBlock> + </AddressSpace> + </Processor> + <Config> + <Option Name="Part" Val="xcu200-fsgd2104-2-e"/> + </Config> + <DRC> + <Rule Name="RDADDRCHANGE" Val="false"/> + </DRC> +</MemInfoSimulation> |