Initial commit

1 files changed, 31 insertions, 0 deletions

diff --git a/projects/U200/verilog/project.vh b/projects/U200/verilog/project.vh
new file mode 100644
index 0000000..8286cbd
--- /dev/null
+++ b/projects/U200/verilog/project.vh
@@ -0,0 +1,31 @@
+`define UDIMM_x8
+
+`ifdef UDIMM_x8
+
+    `define DQ_WIDTH 64
+    `define ODT_WIDTH 2
+    `define CS_WIDTH 2
+    `define CKE_WIDTH 2
+    `define CK_WIDTH 1
+    `define ROW_ADDR_WIDTH 17
+
+`elsif RDIMM_x8
+
+    `define DQ_WIDTH   72
+    `define ODT_WIDTH  2
+    `define CS_WIDTH   2
+    `define CKE_WIDTH  2
+    `define CK_WIDTH   1
+    `define ROW_ADDR_WIDTH 17
+    
+`elsif RDIMM_x4
+
+    `define DQ_WIDTH   72
+    `define ODT_WIDTH  2
+    `define CS_WIDTH   2
+    `define CKE_WIDTH  2
+    `define CK_WIDTH   1
+    `define ROW_ADDR_WIDTH 18
+    
+`endif
+