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diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ip/xdma/xdma_stub.vhdl b/projects/XUPVVH/XUPVVH.ip_user_files/ip/xdma/xdma_stub.vhdl
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+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
+-- Date        : Sun Oct 18 14:34:24 2020
+-- Host        : jalapeno running 64-bit Ubuntu 18.04.5 LTS
+-- Command     : write_vhdl -force -mode synth_stub
+--               /home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.srcs/sources_1/ip/xdma/xdma_stub.vhdl
+-- Design      : xdma
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xcvu37p-fsvh2892-2-e
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity xdma is
+  Port ( 
+    sys_clk : in STD_LOGIC;
+    sys_clk_gt : in STD_LOGIC;
+    sys_rst_n : in STD_LOGIC;
+    user_lnk_up : out STD_LOGIC;
+    pci_exp_txp : out STD_LOGIC_VECTOR ( 7 downto 0 );
+    pci_exp_txn : out STD_LOGIC_VECTOR ( 7 downto 0 );
+    pci_exp_rxp : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    pci_exp_rxn : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    axi_aclk : out STD_LOGIC;
+    axi_aresetn : out STD_LOGIC;
+    usr_irq_req : in STD_LOGIC_VECTOR ( 0 to 0 );
+    usr_irq_ack : out STD_LOGIC_VECTOR ( 0 to 0 );
+    msi_enable : out STD_LOGIC;
+    msi_vector_width : out STD_LOGIC_VECTOR ( 2 downto 0 );
+    cfg_mgmt_addr : in STD_LOGIC_VECTOR ( 18 downto 0 );
+    cfg_mgmt_write : in STD_LOGIC;
+    cfg_mgmt_write_data : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    cfg_mgmt_byte_enable : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    cfg_mgmt_read : in STD_LOGIC;
+    cfg_mgmt_read_data : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    cfg_mgmt_read_write_done : out STD_LOGIC;
+    s_axis_c2h_tdata_0 : in STD_LOGIC_VECTOR ( 255 downto 0 );
+    s_axis_c2h_tlast_0 : in STD_LOGIC;
+    s_axis_c2h_tvalid_0 : in STD_LOGIC;
+    s_axis_c2h_tready_0 : out STD_LOGIC;
+    s_axis_c2h_tkeep_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    m_axis_h2c_tdata_0 : out STD_LOGIC_VECTOR ( 255 downto 0 );
+    m_axis_h2c_tlast_0 : out STD_LOGIC;
+    m_axis_h2c_tvalid_0 : out STD_LOGIC;
+    m_axis_h2c_tready_0 : in STD_LOGIC;
+    m_axis_h2c_tkeep_0 : out STD_LOGIC_VECTOR ( 31 downto 0 )
+  );
+
+end xdma;
+
+architecture stub of xdma is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "sys_clk,sys_clk_gt,sys_rst_n,user_lnk_up,pci_exp_txp[7:0],pci_exp_txn[7:0],pci_exp_rxp[7:0],pci_exp_rxn[7:0],axi_aclk,axi_aresetn,usr_irq_req[0:0],usr_irq_ack[0:0],msi_enable,msi_vector_width[2:0],cfg_mgmt_addr[18:0],cfg_mgmt_write,cfg_mgmt_write_data[31:0],cfg_mgmt_byte_enable[3:0],cfg_mgmt_read,cfg_mgmt_read_data[31:0],cfg_mgmt_read_write_done,s_axis_c2h_tdata_0[255:0],s_axis_c2h_tlast_0,s_axis_c2h_tvalid_0,s_axis_c2h_tready_0,s_axis_c2h_tkeep_0[31:0],m_axis_h2c_tdata_0[255:0],m_axis_h2c_tlast_0,m_axis_h2c_tvalid_0,m_axis_h2c_tready_0,m_axis_h2c_tkeep_0[31:0]";
+attribute X_CORE_INFO : string;
+attribute X_CORE_INFO of stub : architecture is "xdma_core_top,Vivado 2019.2";
+begin
+end;