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| author | Ataberk <olgunataberk@gmail.com> | 2022-09-25 17:22:03 +0200 |
|---|---|---|
| committer | Ataberk <olgunataberk@gmail.com> | 2022-09-25 17:22:03 +0200 |
| commit | dc0b3db1b4f1895a07e5fe280ee3790e87f97b9f (patch) | |
| tree | b47203aa281bdd959def4451c84d310cd9cf2e12 /projects/XUPVVH/verilog/project.vh | |
| download | dram-bender-dc0b3db1b4f1895a07e5fe280ee3790e87f97b9f.tar.gz | |
Initial commit
Diffstat (limited to 'projects/XUPVVH/verilog/project.vh')
| -rw-r--r-- | projects/XUPVVH/verilog/project.vh | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/projects/XUPVVH/verilog/project.vh b/projects/XUPVVH/verilog/project.vh new file mode 100644 index 0000000..4084e1d --- /dev/null +++ b/projects/XUPVVH/verilog/project.vh @@ -0,0 +1,11 @@ +`define XUPP3R_x4// MIG does not support DM|DBI w/ RDIMMs. +`define DQ_WIDTH 72 + +// DIMM related - x8 double ranks +`ifdef XUPP3R_x4 +// DEFAULT CONFIGS USE BELOW +`define ODT_WIDTH 2 +`define CS_WIDTH 2 +`define CKE_WIDTH 2 +`define CK_WIDTH 1 +`endif
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