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| author | Ataberk <olgunataberk@gmail.com> | 2024-05-02 17:22:05 +0200 |
|---|---|---|
| committer | Ataberk <olgunataberk@gmail.com> | 2024-05-02 17:22:05 +0200 |
| commit | 7721980589f4c7fa811689e815a77d63f2556497 (patch) | |
| tree | ded507bcfb0aeddb7ef647dd3888ef93ff12e630 /sources/hdl/header_verilog/parameters.vh | |
| parent | 82b4ae69fa5fa8728b7aa9a513a9a27fb14a5f78 (diff) | |
| download | dram-bender-7721980589f4c7fa811689e815a77d63f2556497.tar.gz | |
Add sources for U50 HBM2
Diffstat (limited to 'sources/hdl/header_verilog/parameters.vh')
| -rw-r--r-- | sources/hdl/header_verilog/parameters.vh | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/sources/hdl/header_verilog/parameters.vh b/sources/hdl/header_verilog/parameters.vh index 916c973..f60c2ad 100644 --- a/sources/hdl/header_verilog/parameters.vh +++ b/sources/hdl/header_verilog/parameters.vh @@ -3,12 +3,13 @@ `define IMEM_ADDR_WIDTH 11 // Decode - Execute -`define DDR_UOP_WIDTH 27 +`define DDR_UOP_WIDTH 31 `define EXE_UOP_WIDTH 62 `define BG_WIDTH 2 `define BANK_WIDTH 2 `define COL_WIDTH 10 `define ROW_WIDTH 17 +`define HBM_CH_WIDTH 4 //Frontend `define XDMA_AXI_DATA_WIDTH 256 |