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| author | Ataberk <olgunataberk@gmail.com> | 2024-05-02 17:22:05 +0200 |
|---|---|---|
| committer | Ataberk <olgunataberk@gmail.com> | 2024-05-02 17:22:05 +0200 |
| commit | 7721980589f4c7fa811689e815a77d63f2556497 (patch) | |
| tree | ded507bcfb0aeddb7ef647dd3888ef93ff12e630 /sources/hdl/verilog/maintenance_controller.v | |
| parent | 82b4ae69fa5fa8728b7aa9a513a9a27fb14a5f78 (diff) | |
| download | dram-bender-7721980589f4c7fa811689e815a77d63f2556497.tar.gz | |
Add sources for U50 HBM2
Diffstat (limited to 'sources/hdl/verilog/maintenance_controller.v')
| -rw-r--r-- | sources/hdl/verilog/maintenance_controller.v | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/sources/hdl/verilog/maintenance_controller.v b/sources/hdl/verilog/maintenance_controller.v index 9354d17..169833a 100644 --- a/sources/hdl/verilog/maintenance_controller.v +++ b/sources/hdl/verilog/maintenance_controller.v @@ -172,8 +172,12 @@ module maintenance_controller#(parameter tCK = 1500)( wire periodic_rd_timer_one = maint_prescaler_tick_r_lcl && (periodic_rd_timer_r == ONE[0+:PERIODIC_RD_TIMER_WIDTH]); + `ifndef HBM_BENDER wire periodic_rd_request = ~rst && (/*((PERIODIC_RD_TIMER_DIV != 0) && ~dfi_init_complete) ||*/ (~per_rd_ack && (per_rd_request || periodic_rd_timer_one))); + `else + wire periodic_rd_request = 1'b0; + `endif always @(posedge clk) begin if(~init_calib_complete) @@ -221,8 +225,12 @@ module maintenance_controller#(parameter tCK = 1500)( always @(posedge clk) zq_request_r <= zq_request_ns; - always @(/*AS*/init_calib_complete or zq_request_r) - zq_request = init_calib_complete && zq_request_r; + always @(/*AS*/init_calib_complete or zq_request_r) + `ifndef HBM_BENDER + zq_request = init_calib_complete && zq_request_r; + `else + zq_request = 1'b0; + `endif end // zq_request_logic end endgenerate |