Initial commit

1 files changed, 33 insertions, 0 deletions

diff --git a/sources/hdl/verilog/reg_mem.v b/sources/hdl/verilog/reg_mem.v
new file mode 100644
index 0000000..a8d37cd
--- /dev/null
+++ b/sources/hdl/verilog/reg_mem.v
@@ -0,0 +1,33 @@
+`timescale 1ns / 1ps
+
+module reg_mem(
+    input [9:0] addr,
+    input clk,
+    input [31:0] din,
+    output [31:0] dout,
+    input en,
+    input we
+    );
+    
+    reg [31:0] mem [1023:0];
+    
+    integer i;
+    initial
+    begin
+        for(i=0; i<1024; i=i+1)
+            mem[i]=0;
+    end
+        
+    reg [31:0] out;
+        
+    assign dout=out;    
+        
+    always @(posedge clk)
+    begin
+        if(we)
+            mem[addr]<=din;
+        else if(en)
+            out<=mem[addr];
+    end
+            
+endmodule