diff options
Diffstat (limited to 'projects/U200/U200.ip_user_files/mem_init_files')
17 files changed, 2952 insertions, 0 deletions
diff --git a/projects/U200/U200.ip_user_files/mem_init_files/custom_parts_ddr4_2016_4_and_above.csv b/projects/U200/U200.ip_user_files/mem_init_files/custom_parts_ddr4_2016_4_and_above.csv new file mode 100755 index 0000000..0e96b29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/mem_init_files/custom_parts_ddr4_2016_4_and_above.csv @@ -0,0 +1,9 @@ +Part type,Part name,Rank,StackHeight,CA Mirror,Data mask,Address width,Row width,Column width,Bank width,Bank group width,CS width,CKE width,ODT width,CK width,Memory speed grade,Memory density,Component density,Memory device width,Memory component width,Data bits per strobe,IO Voltages,Data widths,Min period,Max period,tCKE,tFAW,tFAW_dlr,tMRD,tRAS,tRCD,tREFI,tRFC,tRFC_dlr,tRP,tRRD_S,tRRD_L,tRRD_dlr,tRTP,tWR,tWTR_S,tWTR_L,tXPR,tZQCS,tZQINIT,tCCD_3ds,cas latency,cas write latency,burst length
+Components,DDR4_CUSTOM,1,1,0,1,17,15,10,2,1,1,1,1,1,107E,4Gb,4Gb,16,16,8,1.2V,"8,16,24,32,40,48,56,64,72,80",1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,13,12,8
+UDIMMs,DDR4_CUSTOM1,2,1,1,1,17,15,10,2,2,2,2,2,2,2G1,8GB,1Gb,72,8,8,1.2V,72,1250,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,12,9,8
+SODIMMs,DDR4_CUSTOM2,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,64,8,8,1.2V,64,1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,14,12,8
+RDIMMs,DDR4_CUSTOM3,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,72,8,8,1.2V,72,938,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,15,11,8
+RDIMMs,DDR4_CUSTOM4,2,2,1,1,17,15,10,2,2,2,2,2,1,83,8GB,4Gb,72,8,8,1.2V,72,833,1600,5000 ps,21000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,100000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,4 tck,16,14,8
+RDIMMs,DDR4_CUSTOM5,2,4,1,0,17,16,10,2,2,2,2,2,1,83,16GB,4Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+RDIMMs,64GB,1,1,0,0,18,18,10,2,2,1,1,1,1,83,64GB,16Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+LRDIMMs,DDR4_CUSTOM6,4,1,1,0,17,16,10,2,2,4,2,2,2,093E,32GB,8Gb,72,4,4,1.2V,72,938,1600,5000 ps,15000 ps,0,8 tck,33000 ps,14060 ps,7800000 ps,260000 ps,0,14160 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,15,11,8
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+#ifndef IP_PHY_DDR4_H_ +#define IP_PHY_DDR4_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +#include "phy_ddr4_sc.h" + + + + +#ifdef XILINX_SIMULATOR +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XILINX_SIMULATOR + + + + +#ifdef XM_SYSTEMC +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XM_SYSTEMC + + + + +#ifdef RIVIERA +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // RIVIERA + + + + +#ifdef VCSSYSTEMC +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // VCSSYSTEMC + + + + +#ifdef MTI_SYSTEMC +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // MTI_SYSTEMC +#endif // IP_PHY_DDR4_H_ diff --git a/projects/U200/U200.ip_user_files/mem_init_files/phy_ddr4_sc.h b/projects/U200/U200.ip_user_files/mem_init_files/phy_ddr4_sc.h new file mode 100755 index 0000000..036743e --- /dev/null +++ b/projects/U200/U200.ip_user_files/mem_init_files/phy_ddr4_sc.h @@ -0,0 +1,94 @@ +#ifndef IP_PHY_DDR4_SC_H_ +#define IP_PHY_DDR4_SC_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +class sim_ddr_v2_0; + +class DllExport phy_ddr4_sc : public sc_core::sc_module +{ +public: + + phy_ddr4_sc(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_sc(); + + // module socket-to-socket AXI TLM interfaces + + + // module socket-to-socket TLM interfaces + + +protected: + + sim_ddr_v2_0* mp_impl; + +private: + + phy_ddr4_sc(const phy_ddr4_sc&); + const phy_ddr4_sc& operator=(const phy_ddr4_sc&); + +}; + +#endif // IP_PHY_DDR4_SC_H_ diff --git a/projects/U200/U200.ip_user_files/mem_init_files/phy_ddr4_udimm.h b/projects/U200/U200.ip_user_files/mem_init_files/phy_ddr4_udimm.h new file mode 100755 index 0000000..ec2d0cd --- /dev/null +++ b/projects/U200/U200.ip_user_files/mem_init_files/phy_ddr4_udimm.h @@ -0,0 +1,467 @@ +#ifndef IP_PHY_DDR4_UDIMM_H_ +#define IP_PHY_DDR4_UDIMM_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +#include "phy_ddr4_udimm_sc.h" + + + + +#ifdef XILINX_SIMULATOR +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XILINX_SIMULATOR + + + + +#ifdef XM_SYSTEMC +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XM_SYSTEMC + + + + +#ifdef RIVIERA +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // RIVIERA + + + + +#ifdef VCSSYSTEMC +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // VCSSYSTEMC + + + + +#ifdef MTI_SYSTEMC +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // MTI_SYSTEMC +#endif // IP_PHY_DDR4_UDIMM_H_ diff --git a/projects/U200/U200.ip_user_files/mem_init_files/phy_ddr4_udimm_sc.h b/projects/U200/U200.ip_user_files/mem_init_files/phy_ddr4_udimm_sc.h new file mode 100755 index 0000000..e31f3a2 --- /dev/null +++ b/projects/U200/U200.ip_user_files/mem_init_files/phy_ddr4_udimm_sc.h @@ -0,0 +1,94 @@ +#ifndef IP_PHY_DDR4_UDIMM_SC_H_ +#define IP_PHY_DDR4_UDIMM_SC_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +class sim_ddr_v2_0; + +class DllExport phy_ddr4_udimm_sc : public sc_core::sc_module +{ +public: + + phy_ddr4_udimm_sc(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm_sc(); + + // module socket-to-socket AXI TLM interfaces + + + // module socket-to-socket TLM interfaces + + +protected: + + sim_ddr_v2_0* mp_impl; + +private: + + phy_ddr4_udimm_sc(const phy_ddr4_udimm_sc&); + const phy_ddr4_udimm_sc& operator=(const phy_ddr4_udimm_sc&); + +}; + +#endif // IP_PHY_DDR4_UDIMM_SC_H_ diff --git a/projects/U200/U200.ip_user_files/mem_init_files/phy_rdimm_x8_dual.h b/projects/U200/U200.ip_user_files/mem_init_files/phy_rdimm_x8_dual.h new file mode 100755 index 0000000..ba46738 --- /dev/null +++ b/projects/U200/U200.ip_user_files/mem_init_files/phy_rdimm_x8_dual.h @@ -0,0 +1,477 @@ +#ifndef IP_PHY_RDIMM_X8_DUAL_H_ +#define IP_PHY_RDIMM_X8_DUAL_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +#include "phy_rdimm_x8_dual_sc.h" + + + + +#ifdef XILINX_SIMULATOR +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XILINX_SIMULATOR + + + + +#ifdef XM_SYSTEMC +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XM_SYSTEMC + + + + +#ifdef RIVIERA +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // RIVIERA + + + + +#ifdef VCSSYSTEMC +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // VCSSYSTEMC + + + + +#ifdef MTI_SYSTEMC +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // MTI_SYSTEMC +#endif // IP_PHY_RDIMM_X8_DUAL_H_ diff --git a/projects/U200/U200.ip_user_files/mem_init_files/phy_rdimm_x8_dual_sc.h b/projects/U200/U200.ip_user_files/mem_init_files/phy_rdimm_x8_dual_sc.h new file mode 100755 index 0000000..cdbac59 --- /dev/null +++ b/projects/U200/U200.ip_user_files/mem_init_files/phy_rdimm_x8_dual_sc.h @@ -0,0 +1,94 @@ +#ifndef IP_PHY_RDIMM_X8_DUAL_SC_H_ +#define IP_PHY_RDIMM_X8_DUAL_SC_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +class sim_ddr_v2_0; + +class DllExport phy_rdimm_x8_dual_sc : public sc_core::sc_module +{ +public: + + phy_rdimm_x8_dual_sc(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual_sc(); + + // module socket-to-socket AXI TLM interfaces + + + // module socket-to-socket TLM interfaces + + +protected: + + sim_ddr_v2_0* mp_impl; + +private: + + phy_rdimm_x8_dual_sc(const phy_rdimm_x8_dual_sc&); + const phy_rdimm_x8_dual_sc& operator=(const phy_rdimm_x8_dual_sc&); + +}; + +#endif // IP_PHY_RDIMM_X8_DUAL_SC_H_ diff --git a/projects/U200/U200.ip_user_files/mem_init_files/pr_read.coe b/projects/U200/U200.ip_user_files/mem_init_files/pr_read.coe new file mode 100755 index 0000000..b9ccb93 --- /dev/null +++ b/projects/U200/U200.ip_user_files/mem_init_files/pr_read.coe @@ -0,0 +1,15 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010000000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001011000001100101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001001000001000101, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/U200/U200.ip_user_files/mem_init_files/pr_read_mem.mif b/projects/U200/U200.ip_user_files/mem_init_files/pr_read_mem.mif new file mode 100755 index 0000000..ef3787e --- /dev/null +++ b/projects/U200/U200.ip_user_files/mem_init_files/pr_read_mem.mif @@ -0,0 +1,13 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010000000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001011000001100101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001001000001000101 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/U200/U200.ip_user_files/mem_init_files/pr_ref.coe b/projects/U200/U200.ip_user_files/mem_init_files/pr_ref.coe new file mode 100755 index 0000000..8b0a9e1 --- /dev/null +++ b/projects/U200/U200.ip_user_files/mem_init_files/pr_ref.coe @@ -0,0 +1,51 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001101000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/U200/U200.ip_user_files/mem_init_files/pr_ref_mem.mif b/projects/U200/U200.ip_user_files/mem_init_files/pr_ref_mem.mif new file mode 100755 index 0000000..b3e8583 --- /dev/null +++ b/projects/U200/U200.ip_user_files/mem_init_files/pr_ref_mem.mif @@ -0,0 +1,49 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010100000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001101000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/U200/U200.ip_user_files/mem_init_files/pr_zq.coe b/projects/U200/U200.ip_user_files/mem_init_files/pr_zq.coe new file mode 100755 index 0000000..16d563c --- /dev/null +++ b/projects/U200/U200.ip_user_files/mem_init_files/pr_zq.coe @@ -0,0 +1,42 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001100000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/U200/U200.ip_user_files/mem_init_files/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/mem_init_files/sim_ddr_v2_0.h new file mode 100755 index 0000000..8dc8c75 --- /dev/null +++ b/projects/U200/U200.ip_user_files/mem_init_files/sim_ddr_v2_0.h @@ -0,0 +1,221 @@ +// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +#include "utils/xtlm_cmnhdr.h" +#include "xtlm.h" +#include "report_handler.h" +#include <sstream> +#ifdef SDACCEL_WITH_DATA_CONVERTER +#include "sdaccel_data_converter.h" +#endif +#include "sim_ddrx.h" +#ifdef TLM2_PROTOCOL_CHEKER +#include "tlm2_base_protocol_checker.h" +#endif +#ifndef sim_ddr_v2_0_H +#define sim_ddr_v2_0_H +#include "utils/xsc_stub_port.h" +#include <utils/xtlm_aximm_passthru_module.h> +class sim_ddr_v2_0 :public sc_module{ + public: + explicit sim_ddr_v2_0(sc_core::sc_module_name name, + xsc::common_cpp::properties model_param_props); + ~sim_ddr_v2_0(); + + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket; + + xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util; + xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util; + SC_HAS_PROCESS(sim_ddr_v2_0); + +#ifdef SDACCEL_WITH_DATA_CONVERTER + sdaccel_data_converter* sdaccel_data_converter_model; +#endif + +#ifdef TLM2_PROTOCOL_CHEKER + tlm2_base_protocol_checker* checker; +#endif + sc_core::sc_out<bool> c0_ddr4_ui_clk; + sc_core::sc_in<bool> c0_ddr4_aresetn; + sc_core::sc_in<bool> sys_rst; + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + xsc::utils::xsc_stub_port dbg_bus; + xsc::utils::xsc_stub_port c0_ddr4_adr; + xsc::utils::xsc_stub_port c0_ddr4_ba; + xsc::utils::xsc_stub_port c0_ddr4_cke; + xsc::utils::xsc_stub_port c0_ddr4_cs_n; + xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port c0_ddr4_dq; + xsc::utils::xsc_stub_port c0_ddr4_dqs_c; + xsc::utils::xsc_stub_port c0_ddr4_dqs_t; + xsc::utils::xsc_stub_port c0_ddr4_odt; + xsc::utils::xsc_stub_port c0_ddr4_bg; + xsc::utils::xsc_stub_port c0_ddr4_parity; + xsc::utils::xsc_stub_port c0_ddr4_reset_n; + xsc::utils::xsc_stub_port c0_ddr4_act_n; + xsc::utils::xsc_stub_port c0_ddr4_ck_c; + xsc::utils::xsc_stub_port c0_ddr4_ck_t; + xsc::utils::xsc_stub_port c0_ddr4_interrupt; + xsc::utils::xsc_stub_port addn_ui_clkout1; + xsc::utils::xsc_stub_port dbg_rd_data_cmp; + xsc::utils::xsc_stub_port dbg_expected_data; + xsc::utils::xsc_stub_port dbg_cal_seq; + xsc::utils::xsc_stub_port dbg_cal_seq_cnt; + xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt; + xsc::utils::xsc_stub_port dbg_rd_valid; + xsc::utils::xsc_stub_port dbg_cmp_byte; + xsc::utils::xsc_stub_port dbg_rd_data; + xsc::utils::xsc_stub_port dbg_cplx_config; + xsc::utils::xsc_stub_port dbg_cplx_status; + xsc::utils::xsc_stub_port dbg_io_address; + xsc::utils::xsc_stub_port dbg_pllGate; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp; + xsc::utils::xsc_stub_port cal_r0_status; + xsc::utils::xsc_stub_port cal_post_status; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_en; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete; + xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_req; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack; + xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error; + xsc::utils::xsc_stub_port c0_ddr4_app_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_cmd; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_en; + xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid; + xsc::utils::xsc_stub_port c0_ddr4_app_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy; + xsc::utils::xsc_stub_port rdDataEn; + xsc::utils::xsc_stub_port rdDataEnd; + xsc::utils::xsc_stub_port per_rd_done; + xsc::utils::xsc_stub_port rmw_rd_done; + xsc::utils::xsc_stub_port wrDataEn; + xsc::utils::xsc_stub_port mc_ACT_n; + xsc::utils::xsc_stub_port mcCasSlot; + xsc::utils::xsc_stub_port mcCasSlot2; + xsc::utils::xsc_stub_port mcRdCAS; + xsc::utils::xsc_stub_port mcWrCAS; + xsc::utils::xsc_stub_port winInjTxn; + xsc::utils::xsc_stub_port winRmw; + xsc::utils::xsc_stub_port gt_data_ready; + xsc::utils::xsc_stub_port winRank; + xsc::utils::xsc_stub_port tCWL; + xsc::utils::xsc_stub_port wrData; + xsc::utils::xsc_stub_port wrDataMask; + xsc::utils::xsc_stub_port rdData; + xsc::utils::xsc_stub_port mc_ADR; + xsc::utils::xsc_stub_port mc_BA; + xsc::utils::xsc_stub_port mc_CKE; + xsc::utils::xsc_stub_port mc_CS_n; + xsc::utils::xsc_stub_port mc_ODT; + xsc::utils::xsc_stub_port dBufAdr; + xsc::utils::xsc_stub_port rdDataAddr; + xsc::utils::xsc_stub_port wrDataAddr; + xsc::utils::xsc_stub_port winBuf; + xsc::utils::xsc_stub_port ddr4_act_n; + xsc::utils::xsc_stub_port ddr4_adr; + xsc::utils::xsc_stub_port ddr4_ba; + xsc::utils::xsc_stub_port ddr4_bg; + xsc::utils::xsc_stub_port ddr4_par; + xsc::utils::xsc_stub_port ddr4_cke; + xsc::utils::xsc_stub_port ddr4_odt; + xsc::utils::xsc_stub_port ddr4_cs_n; + xsc::utils::xsc_stub_port ddr4_ck_t; + xsc::utils::xsc_stub_port ddr4_ck_c; + xsc::utils::xsc_stub_port ddr4_reset_n; + xsc::utils::xsc_stub_port ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port ddr4_dq; + xsc::utils::xsc_stub_port ddr4_dqs_c; + xsc::utils::xsc_stub_port ddr4_dqs_t; + xsc::utils::xsc_stub_port mc_BG; + + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > c0_sys_clk_i; + sc_core::sc_signal<bool>out1; + sc_core::sc_signal<bool>out2; + xsc::common_cpp::report_handler* m_report_handler; + std::stringstream m_ss; + float clk; + void generateReset(); + protected: + + private: + xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model; + + std::map<std::string, int> user_param_int; + std::map<std::string, std::string> user_param_string; + +}; +#endif + diff --git a/projects/U200/U200.ip_user_files/mem_init_files/simmem.coe b/projects/U200/U200.ip_user_files/mem_init_files/simmem.coe new file mode 100755 index 0000000..90d215f --- /dev/null +++ b/projects/U200/U200.ip_user_files/mem_init_files/simmem.coe @@ -0,0 +1,398 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0000000000000110000000000000000000000000100010000000000000000000, +0000000000000110000000000000000000000000101100000000000100000000, +0000000000000110000000000000000000000000000000000000000010000000, +0000000000000110000000000000000000000000000100000000000000010000, +0000000000000110000000000000000000000000001000000000000000010000, +0001000000000000000000000000000000000000101000000000000000110000, +0100000000000011000000000000000000000000000000000000000000000011, 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\ No newline at end of file diff --git a/projects/U200/U200.ip_user_files/mem_init_files/summary.log b/projects/U200/U200.ip_user_files/mem_init_files/summary.log new file mode 100755 index 0000000..7930542 --- /dev/null +++ b/projects/U200/U200.ip_user_files/mem_init_files/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [64] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/mem_init_files/zq_calib_mem.mif b/projects/U200/U200.ip_user_files/mem_init_files/zq_calib_mem.mif new file mode 100755 index 0000000..fdf3bb0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/mem_init_files/zq_calib_mem.mif @@ -0,0 +1,40 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010100000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001100000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 |