diff options
Diffstat (limited to 'projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/ies')
5 files changed, 471 insertions, 0 deletions
diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/ies/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/ies/README.txt new file mode 100644 index 0000000..f57b63c --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:48 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./xdma.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './xdma.sh' script. + +./xdma.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./xdma.sh -noclean_files + +For more information on the script, please type './xdma.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/ies/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/ies/file_info.txt new file mode 100644 index 0000000..b680091 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/ies/file_info.txt @@ -0,0 +1,77 @@ +xpm_cdc.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_fifo.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_memory.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_bit_sync.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gte4_drp_arb.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_reset.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_reset_sync.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_reset_inv_sync.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_channel.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_gtye4_channel_wrapper.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtye4_channel_wrapper.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_common.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_gtye4_common_wrapper.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtye4_common_wrapper.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_gtwizard_gtye4.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtwizard_gtye4.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_gtwizard_top.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtwizard_top.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_cxs_remap.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_cxs_remap.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_16k_int.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_16k_int.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_16k.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_16k.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_32k.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_32k.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_4k_int.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_4k_int.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_msix.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_msix.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_rep_int.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_rep_int.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_rep.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_rep.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_tph.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_tph.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gtwizard_top.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gtwizard_top.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_phy_ff_chain.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_ff_chain.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_phy_pipeline.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_pipeline.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_gt_channel.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_gt_channel.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_gt_common.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_gt_common.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_phy_clk.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_clk.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_phy_rst.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_rst.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_phy_rxeq.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_rxeq.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_phy_txeq.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_txeq.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_sync_cell.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sync_cell.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_sync.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sync.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_cdr_ctrl_on_eidle.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_cdr_ctrl_on_eidle.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_receiver_detect_rxterm.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_receiver_detect_rxterm.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_phy_wrapper.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_wrapper.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_phy_top.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_top.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_init_ctrl.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_init_ctrl.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_pl_eq.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pl_eq.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_vf_decode.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_vf_decode.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_vf_decode_attr.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_vf_decode_attr.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_pipe.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pipe.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_seqnum_fifo.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_seqnum_fifo.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_sys_clk_gen_ps.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sys_clk_gen_ps.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_pcie4c_uscale_core_top.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pcie4c_uscale_core_top.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4c_ip.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_4_blk_mem_64_reg_be.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_4_blk_mem_64_reg_be.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_4_blk_mem_64_noreg_be.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_4_blk_mem_64_noreg_be.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_vl_rfs.sv,systemverilog,xdma_v4_1_4,../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap_1024.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_core_top.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/sim/xdma.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/ies/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/ies/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/ies/run.f b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/ies/run.f new file mode 100644 index 0000000..c0e8689 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/ies/run.f @@ -0,0 +1,96 @@ +-makelib ies_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/gtwizard_ultrascale_v1_7_7 \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtye4_channel_wrapper.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtye4_common_wrapper.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtwizard_gtye4.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtwizard_top.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_cxs_remap.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_16k_int.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_16k.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_32k.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_4k_int.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_msix.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_rep_int.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_rep.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_tph.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gtwizard_top.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_ff_chain.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_pipeline.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_gt_channel.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_gt_common.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_clk.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_rst.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_rxeq.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_txeq.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sync_cell.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sync.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_cdr_ctrl_on_eidle.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_receiver_detect_rxterm.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_wrapper.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_top.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_init_ctrl.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pl_eq.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_vf_decode.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_vf_decode_attr.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pipe.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_seqnum_fifo.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sys_clk_gen_ps.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pcie4c_uscale_core_top.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4c_ip.v" \ +-endlib +-makelib ies_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_4_blk_mem_64_reg_be.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_4_blk_mem_64_noreg_be.v" \ +-endlib +-makelib ies_lib/xdma_v4_1_4 -sv \ + "../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv" \ +-endlib +-makelib ies_lib/xil_defaultlib -sv \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/sim/xdma.sv" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/ies/xdma.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/ies/xdma.sh new file mode 100755 index 0000000..4760a80 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/ies/xdma.sh @@ -0,0 +1,179 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : xdma.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:48 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: xdma.sh [-help] +# usage: xdma.sh [-lib_map_path] +# usage: xdma.sh [-noclean_files] +# usage: xdma.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'xdma.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xpm gtwizard_ultrascale_v1_7_7 xil_defaultlib blk_mem_gen_v8_4_4 xdma_v4_1_4) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "xdma.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.xdma \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" \ + +incdir+"$ref_dir/../../../ipstatic/hdl/verilog" \ + +incdir+"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" \ + +incdir+"../../../ipstatic/hdl/verilog" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./xdma.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./xdma.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: xdma.sh [-help]\n\ +Usage: xdma.sh [-lib_map_path]\n\ +Usage: xdma.sh [-reset_run]\n\ +Usage: xdma.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 |