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diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/README.txt new file mode 100644 index 0000000..3cd3d87 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +<current_working_directory>/export_sim/<simulator> + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +<simulation_top>.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +<ip-name>.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/activehdl/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/activehdl/README.txt new file mode 100644 index 0000000..54bedef --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:22:39 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./axis_clock_converter.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './axis_clock_converter.sh' script. + +./axis_clock_converter.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./axis_clock_converter.sh -noclean_files + +For more information on the script, please type './axis_clock_converter.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/activehdl/axis_clock_converter.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/activehdl/axis_clock_converter.sh new file mode 100755 index 0000000..2ce9bed --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/activehdl/axis_clock_converter.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : axis_clock_converter.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:22:39 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: axis_clock_converter.sh [-help] +# usage: axis_clock_converter.sh [-lib_map_path] +# usage: axis_clock_converter.sh [-noclean_files] +# usage: axis_clock_converter.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'axis_clock_converter.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "axis_clock_converter.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./axis_clock_converter.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./axis_clock_converter.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: axis_clock_converter.sh [-help]\n\ +Usage: axis_clock_converter.sh [-lib_map_path]\n\ +Usage: axis_clock_converter.sh [-reset_run]\n\ +Usage: axis_clock_converter.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/activehdl/axis_clock_converter.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/activehdl/axis_clock_converter.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/activehdl/axis_clock_converter.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/activehdl/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/activehdl/compile.do new file mode 100644 index 0000000..34baeeb --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/activehdl/compile.do @@ -0,0 +1,33 @@ +vlib work +vlib activehdl + +vlib activehdl/xpm +vlib activehdl/axis_infrastructure_v1_1_0 +vlib activehdl/axis_clock_converter_v1_1_21 +vlib activehdl/xil_defaultlib + +vmap xpm activehdl/xpm +vmap axis_infrastructure_v1_1_0 activehdl/axis_infrastructure_v1_1_0 +vmap axis_clock_converter_v1_1_21 activehdl/axis_clock_converter_v1_1_21 +vmap xil_defaultlib activehdl/xil_defaultlib + +vlog -work xpm -sv2k12 "+incdir+../../../ipstatic/hdl" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work axis_infrastructure_v1_1_0 -v2k5 "+incdir+../../../ipstatic/hdl" \ +"../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v" \ + +vlog -work axis_clock_converter_v1_1_21 -v2k5 "+incdir+../../../ipstatic/hdl" \ +"../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/hdl" \ +"../../../../XUPVVH.srcs/sources_1/ip/axis_clock_converter/sim/axis_clock_converter.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/activehdl/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/activehdl/file_info.txt new file mode 100644 index 0000000..c9eef2d --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/activehdl/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_fifo.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_memory.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_infrastructure_v1_1_vl_rfs.v,verilog,axis_infrastructure_v1_1_0,../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_clock_converter_v1_1_vl_rfs.v,verilog,axis_clock_converter_v1_1_21,../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_clock_converter.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/axis_clock_converter/sim/axis_clock_converter.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/activehdl/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/activehdl/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/activehdl/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/activehdl/simulate.do new file mode 100644 index 0000000..aba7eac --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+axis_clock_converter -L xpm -L axis_infrastructure_v1_1_0 -L axis_clock_converter_v1_1_21 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.axis_clock_converter xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {axis_clock_converter.udo} + +run -all + +endsim + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/activehdl/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/activehdl/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/ies/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/ies/README.txt new file mode 100644 index 0000000..1729672 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:22:39 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./axis_clock_converter.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './axis_clock_converter.sh' script. + +./axis_clock_converter.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./axis_clock_converter.sh -noclean_files + +For more information on the script, please type './axis_clock_converter.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/ies/axis_clock_converter.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/ies/axis_clock_converter.sh new file mode 100755 index 0000000..f72c8f6 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/ies/axis_clock_converter.sh @@ -0,0 +1,177 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : axis_clock_converter.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:22:39 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: axis_clock_converter.sh [-help] +# usage: axis_clock_converter.sh [-lib_map_path] +# usage: axis_clock_converter.sh [-noclean_files] +# usage: axis_clock_converter.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'axis_clock_converter.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xpm axis_infrastructure_v1_1_0 axis_clock_converter_v1_1_21 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "axis_clock_converter.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.axis_clock_converter \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"$ref_dir/../../../ipstatic/hdl" \ + +incdir+"../../../ipstatic/hdl" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./axis_clock_converter.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./axis_clock_converter.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: axis_clock_converter.sh [-help]\n\ +Usage: axis_clock_converter.sh [-lib_map_path]\n\ +Usage: axis_clock_converter.sh [-reset_run]\n\ +Usage: axis_clock_converter.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/ies/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/ies/file_info.txt new file mode 100644 index 0000000..18625d8 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/ies/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_fifo.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_memory.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_infrastructure_v1_1_vl_rfs.v,verilog,axis_infrastructure_v1_1_0,../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_clock_converter_v1_1_vl_rfs.v,verilog,axis_clock_converter_v1_1_21,../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_clock_converter.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/axis_clock_converter/sim/axis_clock_converter.v,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/ies/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/ies/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/ies/run.f b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/ies/run.f new file mode 100644 index 0000000..b4b62ad --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/ies/run.f @@ -0,0 +1,21 @@ +-makelib ies_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/axis_infrastructure_v1_1_0 \ + "../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v" \ +-endlib +-makelib ies_lib/axis_clock_converter_v1_1_21 \ + "../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/axis_clock_converter/sim/axis_clock_converter.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/modelsim/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/modelsim/README.txt new file mode 100644 index 0000000..54bedef --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:22:39 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./axis_clock_converter.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './axis_clock_converter.sh' script. + +./axis_clock_converter.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./axis_clock_converter.sh -noclean_files + +For more information on the script, please type './axis_clock_converter.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/modelsim/axis_clock_converter.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/modelsim/axis_clock_converter.sh new file mode 100755 index 0000000..5a07ba2 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/modelsim/axis_clock_converter.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : axis_clock_converter.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:22:39 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: axis_clock_converter.sh [-help] +# usage: axis_clock_converter.sh [-lib_map_path] +# usage: axis_clock_converter.sh [-noclean_files] +# usage: axis_clock_converter.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'axis_clock_converter.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "axis_clock_converter.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./axis_clock_converter.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/modelsim" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./axis_clock_converter.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: axis_clock_converter.sh [-help]\n\ +Usage: axis_clock_converter.sh [-lib_map_path]\n\ +Usage: axis_clock_converter.sh [-reset_run]\n\ +Usage: axis_clock_converter.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/modelsim/axis_clock_converter.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/modelsim/axis_clock_converter.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/modelsim/axis_clock_converter.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/modelsim/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/modelsim/compile.do new file mode 100644 index 0000000..24b64ee --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/modelsim/compile.do @@ -0,0 +1,33 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xpm +vlib modelsim_lib/msim/axis_infrastructure_v1_1_0 +vlib modelsim_lib/msim/axis_clock_converter_v1_1_21 +vlib modelsim_lib/msim/xil_defaultlib + +vmap xpm modelsim_lib/msim/xpm +vmap axis_infrastructure_v1_1_0 modelsim_lib/msim/axis_infrastructure_v1_1_0 +vmap axis_clock_converter_v1_1_21 modelsim_lib/msim/axis_clock_converter_v1_1_21 +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xpm -64 -incr -sv "+incdir+../../../ipstatic/hdl" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work axis_infrastructure_v1_1_0 -64 -incr "+incdir+../../../ipstatic/hdl" \ +"../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v" \ + +vlog -work axis_clock_converter_v1_1_21 -64 -incr "+incdir+../../../ipstatic/hdl" \ +"../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v" \ + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../ipstatic/hdl" \ +"../../../../XUPVVH.srcs/sources_1/ip/axis_clock_converter/sim/axis_clock_converter.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/modelsim/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/modelsim/file_info.txt new file mode 100644 index 0000000..c9eef2d --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/modelsim/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_fifo.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_memory.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_infrastructure_v1_1_vl_rfs.v,verilog,axis_infrastructure_v1_1_0,../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_clock_converter_v1_1_vl_rfs.v,verilog,axis_clock_converter_v1_1_21,../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_clock_converter.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/axis_clock_converter/sim/axis_clock_converter.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/modelsim/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/modelsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/modelsim/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/modelsim/simulate.do new file mode 100644 index 0000000..ccd294c --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xpm -L axis_infrastructure_v1_1_0 -L axis_clock_converter_v1_1_21 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.axis_clock_converter xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {axis_clock_converter.udo} + +run -all + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/modelsim/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/modelsim/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/questa/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/questa/README.txt new file mode 100644 index 0000000..54bedef --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:22:39 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./axis_clock_converter.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './axis_clock_converter.sh' script. + +./axis_clock_converter.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./axis_clock_converter.sh -noclean_files + +For more information on the script, please type './axis_clock_converter.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/questa/axis_clock_converter.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/questa/axis_clock_converter.sh new file mode 100755 index 0000000..4dd6dc7 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/questa/axis_clock_converter.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : axis_clock_converter.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:22:39 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: axis_clock_converter.sh [-help] +# usage: axis_clock_converter.sh [-lib_map_path] +# usage: axis_clock_converter.sh [-noclean_files] +# usage: axis_clock_converter.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'axis_clock_converter.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "axis_clock_converter.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./axis_clock_converter.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./axis_clock_converter.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: axis_clock_converter.sh [-help]\n\ +Usage: axis_clock_converter.sh [-lib_map_path]\n\ +Usage: axis_clock_converter.sh [-reset_run]\n\ +Usage: axis_clock_converter.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/questa/axis_clock_converter.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/questa/axis_clock_converter.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/questa/axis_clock_converter.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/questa/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/questa/compile.do new file mode 100644 index 0000000..638df96 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/questa/compile.do @@ -0,0 +1,33 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xpm +vlib questa_lib/msim/axis_infrastructure_v1_1_0 +vlib questa_lib/msim/axis_clock_converter_v1_1_21 +vlib questa_lib/msim/xil_defaultlib + +vmap xpm questa_lib/msim/xpm +vmap axis_infrastructure_v1_1_0 questa_lib/msim/axis_infrastructure_v1_1_0 +vmap axis_clock_converter_v1_1_21 questa_lib/msim/axis_clock_converter_v1_1_21 +vmap xil_defaultlib questa_lib/msim/xil_defaultlib + +vlog -work xpm -64 -sv "+incdir+../../../ipstatic/hdl" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work axis_infrastructure_v1_1_0 -64 "+incdir+../../../ipstatic/hdl" \ +"../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v" \ + +vlog -work axis_clock_converter_v1_1_21 -64 "+incdir+../../../ipstatic/hdl" \ +"../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../ipstatic/hdl" \ +"../../../../XUPVVH.srcs/sources_1/ip/axis_clock_converter/sim/axis_clock_converter.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/questa/elaborate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/questa/elaborate.do new file mode 100644 index 0000000..ab01acd --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xpm -L axis_infrastructure_v1_1_0 -L axis_clock_converter_v1_1_21 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.axis_clock_converter xil_defaultlib.glbl -o axis_clock_converter_opt diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/questa/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/questa/file_info.txt new file mode 100644 index 0000000..c9eef2d --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/questa/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_fifo.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_memory.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_infrastructure_v1_1_vl_rfs.v,verilog,axis_infrastructure_v1_1_0,../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_clock_converter_v1_1_vl_rfs.v,verilog,axis_clock_converter_v1_1_21,../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_clock_converter.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/axis_clock_converter/sim/axis_clock_converter.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/questa/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/questa/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/questa/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/questa/simulate.do new file mode 100644 index 0000000..a79020d --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib axis_clock_converter_opt + +do {wave.do} + +view wave +view structure +view signals + +do {axis_clock_converter.udo} + +run -all + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/questa/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/questa/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/riviera/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/riviera/README.txt new file mode 100644 index 0000000..54bedef --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:22:39 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./axis_clock_converter.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './axis_clock_converter.sh' script. + +./axis_clock_converter.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./axis_clock_converter.sh -noclean_files + +For more information on the script, please type './axis_clock_converter.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/riviera/axis_clock_converter.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/riviera/axis_clock_converter.sh new file mode 100755 index 0000000..1481fd0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/riviera/axis_clock_converter.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : axis_clock_converter.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:22:39 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: axis_clock_converter.sh [-help] +# usage: axis_clock_converter.sh [-lib_map_path] +# usage: axis_clock_converter.sh [-noclean_files] +# usage: axis_clock_converter.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'axis_clock_converter.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "axis_clock_converter.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./axis_clock_converter.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./axis_clock_converter.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: axis_clock_converter.sh [-help]\n\ +Usage: axis_clock_converter.sh [-lib_map_path]\n\ +Usage: axis_clock_converter.sh [-reset_run]\n\ +Usage: axis_clock_converter.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/riviera/axis_clock_converter.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/riviera/axis_clock_converter.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/riviera/axis_clock_converter.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/riviera/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/riviera/compile.do new file mode 100644 index 0000000..d6bff82 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/riviera/compile.do @@ -0,0 +1,33 @@ +vlib work +vlib riviera + +vlib riviera/xpm +vlib riviera/axis_infrastructure_v1_1_0 +vlib riviera/axis_clock_converter_v1_1_21 +vlib riviera/xil_defaultlib + +vmap xpm riviera/xpm +vmap axis_infrastructure_v1_1_0 riviera/axis_infrastructure_v1_1_0 +vmap axis_clock_converter_v1_1_21 riviera/axis_clock_converter_v1_1_21 +vmap xil_defaultlib riviera/xil_defaultlib + +vlog -work xpm -sv2k12 "+incdir+../../../ipstatic/hdl" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work axis_infrastructure_v1_1_0 -v2k5 "+incdir+../../../ipstatic/hdl" \ +"../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v" \ + +vlog -work axis_clock_converter_v1_1_21 -v2k5 "+incdir+../../../ipstatic/hdl" \ +"../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/hdl" \ +"../../../../XUPVVH.srcs/sources_1/ip/axis_clock_converter/sim/axis_clock_converter.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/riviera/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/riviera/file_info.txt new file mode 100644 index 0000000..c9eef2d --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/riviera/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_fifo.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_memory.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_infrastructure_v1_1_vl_rfs.v,verilog,axis_infrastructure_v1_1_0,../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_clock_converter_v1_1_vl_rfs.v,verilog,axis_clock_converter_v1_1_21,../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_clock_converter.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/axis_clock_converter/sim/axis_clock_converter.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/riviera/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/riviera/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/riviera/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/riviera/simulate.do new file mode 100644 index 0000000..aba7eac --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+axis_clock_converter -L xpm -L axis_infrastructure_v1_1_0 -L axis_clock_converter_v1_1_21 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.axis_clock_converter xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {axis_clock_converter.udo} + +run -all + +endsim + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/riviera/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/riviera/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/vcs/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/vcs/README.txt new file mode 100644 index 0000000..54bedef --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:22:39 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./axis_clock_converter.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './axis_clock_converter.sh' script. + +./axis_clock_converter.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./axis_clock_converter.sh -noclean_files + +For more information on the script, please type './axis_clock_converter.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/vcs/axis_clock_converter.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/vcs/axis_clock_converter.sh new file mode 100755 index 0000000..167c0b9 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/vcs/axis_clock_converter.sh @@ -0,0 +1,239 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : axis_clock_converter.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:22:39 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: axis_clock_converter.sh [-help] +# usage: axis_clock_converter.sh [-lib_map_path] +# usage: axis_clock_converter.sh [-noclean_files] +# usage: axis_clock_converter.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'axis_clock_converter.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xpm axis_infrastructure_v1_1_0 axis_clock_converter_v1_1_21 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "axis_clock_converter.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + vlogan -work xpm $vlogan_opts -sverilog +incdir+"$ref_dir/../../../ipstatic/hdl" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work axis_infrastructure_v1_1_0 $vlogan_opts +v2k +incdir+"$ref_dir/../../../ipstatic/hdl" \ + "$ref_dir/../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work axis_clock_converter_v1_1_21 $vlogan_opts +v2k +incdir+"$ref_dir/../../../ipstatic/hdl" \ + "$ref_dir/../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ipstatic/hdl" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/axis_clock_converter/sim/axis_clock_converter.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.axis_clock_converter xil_defaultlib.glbl -o axis_clock_converter_simv +} + +# RUN_STEP: <simulate> +simulate() +{ + ./axis_clock_converter_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./axis_clock_converter.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/vcs" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key axis_clock_converter_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc axis_clock_converter_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./axis_clock_converter.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: axis_clock_converter.sh [-help]\n\ +Usage: axis_clock_converter.sh [-lib_map_path]\n\ +Usage: axis_clock_converter.sh [-reset_run]\n\ +Usage: axis_clock_converter.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/vcs/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/vcs/file_info.txt new file mode 100644 index 0000000..18625d8 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/vcs/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_fifo.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_memory.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_infrastructure_v1_1_vl_rfs.v,verilog,axis_infrastructure_v1_1_0,../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_clock_converter_v1_1_vl_rfs.v,verilog,axis_clock_converter_v1_1_21,../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_clock_converter.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/axis_clock_converter/sim/axis_clock_converter.v,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/vcs/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/vcs/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/vcs/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/vcs/simulate.do new file mode 100644 index 0000000..58afc78 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xcelium/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xcelium/README.txt new file mode 100644 index 0000000..1729672 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:22:39 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./axis_clock_converter.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './axis_clock_converter.sh' script. + +./axis_clock_converter.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./axis_clock_converter.sh -noclean_files + +For more information on the script, please type './axis_clock_converter.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xcelium/axis_clock_converter.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xcelium/axis_clock_converter.sh new file mode 100755 index 0000000..2085855 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xcelium/axis_clock_converter.sh @@ -0,0 +1,177 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : axis_clock_converter.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:22:39 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: axis_clock_converter.sh [-help] +# usage: axis_clock_converter.sh [-lib_map_path] +# usage: axis_clock_converter.sh [-noclean_files] +# usage: axis_clock_converter.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'axis_clock_converter.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xpm axis_infrastructure_v1_1_0 axis_clock_converter_v1_1_21 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "axis_clock_converter.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.axis_clock_converter \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"$ref_dir/../../../ipstatic/hdl" \ + +incdir+"../../../ipstatic/hdl" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./axis_clock_converter.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./axis_clock_converter.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: axis_clock_converter.sh [-help]\n\ +Usage: axis_clock_converter.sh [-lib_map_path]\n\ +Usage: axis_clock_converter.sh [-reset_run]\n\ +Usage: axis_clock_converter.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xcelium/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xcelium/file_info.txt new file mode 100644 index 0000000..18625d8 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xcelium/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_fifo.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_memory.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_infrastructure_v1_1_vl_rfs.v,verilog,axis_infrastructure_v1_1_0,../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_clock_converter_v1_1_vl_rfs.v,verilog,axis_clock_converter_v1_1_21,../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_clock_converter.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/axis_clock_converter/sim/axis_clock_converter.v,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xcelium/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xcelium/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xcelium/run.f b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xcelium/run.f new file mode 100644 index 0000000..33c91ec --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xcelium/run.f @@ -0,0 +1,21 @@ +-makelib xcelium_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/axis_infrastructure_v1_1_0 \ + "../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v" \ +-endlib +-makelib xcelium_lib/axis_clock_converter_v1_1_21 \ + "../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/axis_clock_converter/sim/axis_clock_converter.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xsim/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xsim/README.txt new file mode 100644 index 0000000..54bedef --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:22:39 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./axis_clock_converter.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './axis_clock_converter.sh' script. + +./axis_clock_converter.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./axis_clock_converter.sh -noclean_files + +For more information on the script, please type './axis_clock_converter.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xsim/XUPVVH.smi b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xsim/XUPVVH.smi new file mode 100644 index 0000000..7951bb9 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xsim/XUPVVH.smi @@ -0,0 +1,30 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2019.2 (64-bit) --> +<!-- SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 --> +<!-- --> +<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --> +<!-- Nov 6 2019 --> +<!-- --> +<!-- This file is generated by the software with the Tcl write_mem_info command. --> +<!-- Do not edit this file. --> + +<MemInfoSimulation Version="1" Minor="1"> + <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I"> + <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_ADDR_SPACE" ECC="NONE" Begin="0" End="98303"> + <BusBlock> + <BitLane MemType="lmb_bram_I_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303"> + <DataWidth MSB="31" LSB="0"/> + <AddressRange Begin="0" End="16383"/> + <Parity ON="false" NumBits="0"/> + <MemFile Name="bd_9f2c_lmb_bram_I_0.mem"/> + </BitLane> + </BusBlock> + </AddressSpace> + </Processor> + <Config> + <Option Name="Part" Val="xcvu37p-fsvh2892-2-e"/> + </Config> + <DRC> + <Rule Name="RDADDRCHANGE" Val="false"/> + </DRC> +</MemInfoSimulation> diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xsim/axis_clock_converter.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xsim/axis_clock_converter.sh new file mode 100755 index 0000000..f1e1054 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xsim/axis_clock_converter.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : axis_clock_converter.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:22:39 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: axis_clock_converter.sh [-help] +# usage: axis_clock_converter.sh [-lib_map_path] +# usage: axis_clock_converter.sh [-noclean_files] +# usage: axis_clock_converter.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.2/tps/boost_1_64_0 +xvlog_opts="--relax" + + +# Script info +echo -e "axis_clock_converter.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + xelab --relax --debug typical --mt auto -L axis_infrastructure_v1_1_0 -L axis_clock_converter_v1_1_21 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot axis_clock_converter xil_defaultlib.axis_clock_converter xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + xsim axis_clock_converter -key {Behavioral:sim_1:Functional:axis_clock_converter} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./axis_clock_converter.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.2/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=(xil_defaultlib) + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb axis_clock_converter.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./axis_clock_converter.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: axis_clock_converter.sh [-help]\n\ +Usage: axis_clock_converter.sh [-lib_map_path]\n\ +Usage: axis_clock_converter.sh [-reset_run]\n\ +Usage: axis_clock_converter.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xsim/cmd.tcl b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xsim/cmd.tcl new file mode 100644 index 0000000..eef7a0f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xsim/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xsim/file_info.txt new file mode 100644 index 0000000..3ab3444 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xsim/file_info.txt @@ -0,0 +1,2 @@ +axis_clock_converter.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/axis_clock_converter/sim/axis_clock_converter.v,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xsim/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xsim/protoinst_files/bd_9f2c.protoinst b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xsim/protoinst_files/bd_9f2c.protoinst new file mode 100644 index 0000000..cf73fce --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xsim/protoinst_files/bd_9f2c.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_9f2c": { + "proto_instances": { + } + } + } +} diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xsim/vlog.prj b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xsim/vlog.prj new file mode 100644 index 0000000..84710a6 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib --include "../../../ipstatic/hdl" \ +"../../../../XUPVVH.srcs/sources_1/ip/axis_clock_converter/sim/axis_clock_converter.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/README.txt new file mode 100644 index 0000000..3cd3d87 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +<current_working_directory>/export_sim/<simulator> + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +<simulation_top>.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +<ip-name>.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/activehdl/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/activehdl/README.txt new file mode 100644 index 0000000..e6bcc83 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:22:52 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./instr_blk_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './instr_blk_mem.sh' script. + +./instr_blk_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./instr_blk_mem.sh -noclean_files + +For more information on the script, please type './instr_blk_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/activehdl/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/activehdl/compile.do new file mode 100644 index 0000000..c17b527 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/activehdl/compile.do @@ -0,0 +1,28 @@ +vlib work +vlib activehdl + +vlib activehdl/xpm +vlib activehdl/blk_mem_gen_v8_4_4 +vlib activehdl/xil_defaultlib + +vmap xpm activehdl/xpm +vmap blk_mem_gen_v8_4_4 activehdl/blk_mem_gen_v8_4_4 +vmap xil_defaultlib activehdl/xil_defaultlib + +vlog -work xpm -sv2k12 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 \ +"../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/activehdl/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/activehdl/file_info.txt new file mode 100644 index 0000000..dda6091 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/activehdl/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +instr_blk_mem.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/activehdl/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/activehdl/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/activehdl/instr_blk_mem.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/activehdl/instr_blk_mem.sh new file mode 100755 index 0000000..85ea797 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/activehdl/instr_blk_mem.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : instr_blk_mem.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:22:52 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: instr_blk_mem.sh [-help] +# usage: instr_blk_mem.sh [-lib_map_path] +# usage: instr_blk_mem.sh [-noclean_files] +# usage: instr_blk_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'instr_blk_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "instr_blk_mem.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: instr_blk_mem.sh [-help]\n\ +Usage: instr_blk_mem.sh [-lib_map_path]\n\ +Usage: instr_blk_mem.sh [-reset_run]\n\ +Usage: instr_blk_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/activehdl/instr_blk_mem.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/activehdl/instr_blk_mem.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/activehdl/instr_blk_mem.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/activehdl/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/activehdl/simulate.do new file mode 100644 index 0000000..505caff --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+instr_blk_mem -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.instr_blk_mem xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {instr_blk_mem.udo} + +run -all + +endsim + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/activehdl/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/activehdl/summary.log new file mode 100755 index 0000000..5094079 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/activehdl/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [2048] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [4] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 7.524303 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/activehdl/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/activehdl/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/ies/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/ies/README.txt new file mode 100644 index 0000000..8c7504d --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:22:52 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./instr_blk_mem.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './instr_blk_mem.sh' script. + +./instr_blk_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./instr_blk_mem.sh -noclean_files + +For more information on the script, please type './instr_blk_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/ies/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/ies/file_info.txt new file mode 100644 index 0000000..dda6091 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/ies/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +instr_blk_mem.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/ies/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/ies/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/ies/instr_blk_mem.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/ies/instr_blk_mem.sh new file mode 100755 index 0000000..d365b90 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/ies/instr_blk_mem.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : instr_blk_mem.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:22:52 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: instr_blk_mem.sh [-help] +# usage: instr_blk_mem.sh [-lib_map_path] +# usage: instr_blk_mem.sh [-noclean_files] +# usage: instr_blk_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'instr_blk_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "instr_blk_mem.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.instr_blk_mem \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: instr_blk_mem.sh [-help]\n\ +Usage: instr_blk_mem.sh [-lib_map_path]\n\ +Usage: instr_blk_mem.sh [-reset_run]\n\ +Usage: instr_blk_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/ies/run.f b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/ies/run.f new file mode 100644 index 0000000..4643ca5 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/ies/run.f @@ -0,0 +1,18 @@ +-makelib ies_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/ies/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/ies/summary.log new file mode 100755 index 0000000..5094079 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/ies/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [2048] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [4] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 7.524303 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/modelsim/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/modelsim/README.txt new file mode 100644 index 0000000..e6bcc83 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:22:52 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./instr_blk_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './instr_blk_mem.sh' script. + +./instr_blk_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./instr_blk_mem.sh -noclean_files + +For more information on the script, please type './instr_blk_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/modelsim/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/modelsim/compile.do new file mode 100644 index 0000000..670e382 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/modelsim/compile.do @@ -0,0 +1,28 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xpm +vlib modelsim_lib/msim/blk_mem_gen_v8_4_4 +vlib modelsim_lib/msim/xil_defaultlib + +vmap xpm modelsim_lib/msim/xpm +vmap blk_mem_gen_v8_4_4 modelsim_lib/msim/blk_mem_gen_v8_4_4 +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xpm -64 -incr -sv \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -64 -incr \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 -incr \ +"../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/modelsim/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/modelsim/file_info.txt new file mode 100644 index 0000000..dda6091 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/modelsim/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +instr_blk_mem.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/modelsim/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/modelsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/modelsim/instr_blk_mem.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/modelsim/instr_blk_mem.sh new file mode 100755 index 0000000..4c82b20 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/modelsim/instr_blk_mem.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : instr_blk_mem.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:22:52 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: instr_blk_mem.sh [-help] +# usage: instr_blk_mem.sh [-lib_map_path] +# usage: instr_blk_mem.sh [-noclean_files] +# usage: instr_blk_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'instr_blk_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "instr_blk_mem.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/modelsim" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: instr_blk_mem.sh [-help]\n\ +Usage: instr_blk_mem.sh [-lib_map_path]\n\ +Usage: instr_blk_mem.sh [-reset_run]\n\ +Usage: instr_blk_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/modelsim/instr_blk_mem.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/modelsim/instr_blk_mem.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/modelsim/instr_blk_mem.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/modelsim/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/modelsim/simulate.do new file mode 100644 index 0000000..661fc2a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.instr_blk_mem xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {instr_blk_mem.udo} + +run -all + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/modelsim/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/modelsim/summary.log new file mode 100755 index 0000000..5094079 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/modelsim/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [2048] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [4] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 7.524303 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/modelsim/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/modelsim/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/questa/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/questa/README.txt new file mode 100644 index 0000000..e6bcc83 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:22:52 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./instr_blk_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './instr_blk_mem.sh' script. + +./instr_blk_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./instr_blk_mem.sh -noclean_files + +For more information on the script, please type './instr_blk_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/questa/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/questa/compile.do new file mode 100644 index 0000000..ff9ce3c --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/questa/compile.do @@ -0,0 +1,28 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xpm +vlib questa_lib/msim/blk_mem_gen_v8_4_4 +vlib questa_lib/msim/xil_defaultlib + +vmap xpm questa_lib/msim/xpm +vmap blk_mem_gen_v8_4_4 questa_lib/msim/blk_mem_gen_v8_4_4 +vmap xil_defaultlib questa_lib/msim/xil_defaultlib + +vlog -work xpm -64 -sv \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -64 \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 \ +"../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/questa/elaborate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/questa/elaborate.do new file mode 100644 index 0000000..8419996 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.instr_blk_mem xil_defaultlib.glbl -o instr_blk_mem_opt diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/questa/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/questa/file_info.txt new file mode 100644 index 0000000..dda6091 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/questa/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +instr_blk_mem.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/questa/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/questa/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/questa/instr_blk_mem.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/questa/instr_blk_mem.sh new file mode 100755 index 0000000..2ed268f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/questa/instr_blk_mem.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : instr_blk_mem.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:22:52 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: instr_blk_mem.sh [-help] +# usage: instr_blk_mem.sh [-lib_map_path] +# usage: instr_blk_mem.sh [-noclean_files] +# usage: instr_blk_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'instr_blk_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "instr_blk_mem.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: instr_blk_mem.sh [-help]\n\ +Usage: instr_blk_mem.sh [-lib_map_path]\n\ +Usage: instr_blk_mem.sh [-reset_run]\n\ +Usage: instr_blk_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/questa/instr_blk_mem.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/questa/instr_blk_mem.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/questa/instr_blk_mem.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/questa/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/questa/simulate.do new file mode 100644 index 0000000..f514670 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib instr_blk_mem_opt + +do {wave.do} + +view wave +view structure +view signals + +do {instr_blk_mem.udo} + +run -all + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/questa/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/questa/summary.log new file mode 100755 index 0000000..5094079 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/questa/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [2048] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [4] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 7.524303 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/questa/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/questa/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/riviera/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/riviera/README.txt new file mode 100644 index 0000000..e6bcc83 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:22:52 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./instr_blk_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './instr_blk_mem.sh' script. + +./instr_blk_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./instr_blk_mem.sh -noclean_files + +For more information on the script, please type './instr_blk_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/riviera/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/riviera/compile.do new file mode 100644 index 0000000..9a16d68 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/riviera/compile.do @@ -0,0 +1,28 @@ +vlib work +vlib riviera + +vlib riviera/xpm +vlib riviera/blk_mem_gen_v8_4_4 +vlib riviera/xil_defaultlib + +vmap xpm riviera/xpm +vmap blk_mem_gen_v8_4_4 riviera/blk_mem_gen_v8_4_4 +vmap xil_defaultlib riviera/xil_defaultlib + +vlog -work xpm -sv2k12 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 \ +"../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/riviera/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/riviera/file_info.txt new file mode 100644 index 0000000..dda6091 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/riviera/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +instr_blk_mem.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/riviera/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/riviera/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/riviera/instr_blk_mem.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/riviera/instr_blk_mem.sh new file mode 100755 index 0000000..adf6d20 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/riviera/instr_blk_mem.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : instr_blk_mem.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:22:52 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: instr_blk_mem.sh [-help] +# usage: instr_blk_mem.sh [-lib_map_path] +# usage: instr_blk_mem.sh [-noclean_files] +# usage: instr_blk_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'instr_blk_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "instr_blk_mem.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: instr_blk_mem.sh [-help]\n\ +Usage: instr_blk_mem.sh [-lib_map_path]\n\ +Usage: instr_blk_mem.sh [-reset_run]\n\ +Usage: instr_blk_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/riviera/instr_blk_mem.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/riviera/instr_blk_mem.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/riviera/instr_blk_mem.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/riviera/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/riviera/simulate.do new file mode 100644 index 0000000..505caff --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+instr_blk_mem -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.instr_blk_mem xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {instr_blk_mem.udo} + +run -all + +endsim + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/riviera/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/riviera/summary.log new file mode 100755 index 0000000..5094079 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/riviera/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [2048] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [4] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 7.524303 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/riviera/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/riviera/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/vcs/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/vcs/README.txt new file mode 100644 index 0000000..e6bcc83 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:22:52 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./instr_blk_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './instr_blk_mem.sh' script. + +./instr_blk_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./instr_blk_mem.sh -noclean_files + +For more information on the script, please type './instr_blk_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/vcs/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/vcs/file_info.txt new file mode 100644 index 0000000..dda6091 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/vcs/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +instr_blk_mem.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/vcs/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/vcs/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/vcs/instr_blk_mem.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/vcs/instr_blk_mem.sh new file mode 100755 index 0000000..0c20e47 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/vcs/instr_blk_mem.sh @@ -0,0 +1,235 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : instr_blk_mem.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:22:52 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: instr_blk_mem.sh [-help] +# usage: instr_blk_mem.sh [-lib_map_path] +# usage: instr_blk_mem.sh [-noclean_files] +# usage: instr_blk_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'instr_blk_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "instr_blk_mem.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + vlogan -work xpm $vlogan_opts -sverilog \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work blk_mem_gen_v8_4_4 $vlogan_opts +v2k \ + "$ref_dir/../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.instr_blk_mem xil_defaultlib.glbl -o instr_blk_mem_simv +} + +# RUN_STEP: <simulate> +simulate() +{ + ./instr_blk_mem_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/vcs" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key instr_blk_mem_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc instr_blk_mem_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: instr_blk_mem.sh [-help]\n\ +Usage: instr_blk_mem.sh [-lib_map_path]\n\ +Usage: instr_blk_mem.sh [-reset_run]\n\ +Usage: instr_blk_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/vcs/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/vcs/simulate.do new file mode 100644 index 0000000..58afc78 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/vcs/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/vcs/summary.log new file mode 100755 index 0000000..5094079 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/vcs/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [2048] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [4] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 7.524303 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xcelium/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xcelium/README.txt new file mode 100644 index 0000000..8c7504d --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:22:52 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./instr_blk_mem.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './instr_blk_mem.sh' script. + +./instr_blk_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./instr_blk_mem.sh -noclean_files + +For more information on the script, please type './instr_blk_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xcelium/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xcelium/file_info.txt new file mode 100644 index 0000000..dda6091 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xcelium/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +instr_blk_mem.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xcelium/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xcelium/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xcelium/instr_blk_mem.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xcelium/instr_blk_mem.sh new file mode 100755 index 0000000..12a89b2 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xcelium/instr_blk_mem.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : instr_blk_mem.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:22:52 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: instr_blk_mem.sh [-help] +# usage: instr_blk_mem.sh [-lib_map_path] +# usage: instr_blk_mem.sh [-noclean_files] +# usage: instr_blk_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'instr_blk_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "instr_blk_mem.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.instr_blk_mem \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: instr_blk_mem.sh [-help]\n\ +Usage: instr_blk_mem.sh [-lib_map_path]\n\ +Usage: instr_blk_mem.sh [-reset_run]\n\ +Usage: instr_blk_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xcelium/run.f b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xcelium/run.f new file mode 100644 index 0000000..41a497f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xcelium/run.f @@ -0,0 +1,18 @@ +-makelib xcelium_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xcelium/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xcelium/summary.log new file mode 100755 index 0000000..5094079 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xcelium/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [2048] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [4] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 7.524303 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xsim/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xsim/README.txt new file mode 100644 index 0000000..e6bcc83 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:22:52 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./instr_blk_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './instr_blk_mem.sh' script. + +./instr_blk_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./instr_blk_mem.sh -noclean_files + +For more information on the script, please type './instr_blk_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xsim/XUPVVH.smi b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xsim/XUPVVH.smi new file mode 100644 index 0000000..7951bb9 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xsim/XUPVVH.smi @@ -0,0 +1,30 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2019.2 (64-bit) --> +<!-- SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 --> +<!-- --> +<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --> +<!-- Nov 6 2019 --> +<!-- --> +<!-- This file is generated by the software with the Tcl write_mem_info command. --> +<!-- Do not edit this file. --> + +<MemInfoSimulation Version="1" Minor="1"> + <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I"> + <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_ADDR_SPACE" ECC="NONE" Begin="0" End="98303"> + <BusBlock> + <BitLane MemType="lmb_bram_I_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303"> + <DataWidth MSB="31" LSB="0"/> + <AddressRange Begin="0" End="16383"/> + <Parity ON="false" NumBits="0"/> + <MemFile Name="bd_9f2c_lmb_bram_I_0.mem"/> + </BitLane> + </BusBlock> + </AddressSpace> + </Processor> + <Config> + <Option Name="Part" Val="xcvu37p-fsvh2892-2-e"/> + </Config> + <DRC> + <Rule Name="RDADDRCHANGE" Val="false"/> + </DRC> +</MemInfoSimulation> diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xsim/cmd.tcl b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xsim/cmd.tcl new file mode 100644 index 0000000..eef7a0f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xsim/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xsim/file_info.txt new file mode 100644 index 0000000..7f61078 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xsim/file_info.txt @@ -0,0 +1,2 @@ +instr_blk_mem.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xsim/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xsim/instr_blk_mem.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xsim/instr_blk_mem.sh new file mode 100755 index 0000000..a3ab05a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xsim/instr_blk_mem.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : instr_blk_mem.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:22:52 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: instr_blk_mem.sh [-help] +# usage: instr_blk_mem.sh [-lib_map_path] +# usage: instr_blk_mem.sh [-noclean_files] +# usage: instr_blk_mem.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.2/tps/boost_1_64_0 +xvlog_opts="--relax" + + +# Script info +echo -e "instr_blk_mem.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + xelab --relax --debug typical --mt auto -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot instr_blk_mem xil_defaultlib.instr_blk_mem xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + xsim instr_blk_mem -key {Behavioral:sim_1:Functional:instr_blk_mem} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.2/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb instr_blk_mem.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: instr_blk_mem.sh [-help]\n\ +Usage: instr_blk_mem.sh [-lib_map_path]\n\ +Usage: instr_blk_mem.sh [-reset_run]\n\ +Usage: instr_blk_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xsim/protoinst_files/bd_9f2c.protoinst b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xsim/protoinst_files/bd_9f2c.protoinst new file mode 100644 index 0000000..cf73fce --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xsim/protoinst_files/bd_9f2c.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_9f2c": { + "proto_instances": { + } + } + } +} diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xsim/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xsim/summary.log new file mode 100755 index 0000000..5094079 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xsim/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [2048] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [4] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 7.524303 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xsim/vlog.prj b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xsim/vlog.prj new file mode 100644 index 0000000..418e20e --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib \ +"../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/README.txt new file mode 100644 index 0000000..3cd3d87 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +<current_working_directory>/export_sim/<simulator> + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +<simulation_top>.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +<ip-name>.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/README.txt new file mode 100644 index 0000000..ce72be2 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:01 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./instr_blk_mem_sim.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './instr_blk_mem_sim.sh' script. + +./instr_blk_mem_sim.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./instr_blk_mem_sim.sh -noclean_files + +For more information on the script, please type './instr_blk_mem_sim.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/compile.do new file mode 100644 index 0000000..1853822 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/compile.do @@ -0,0 +1,28 @@ +vlib work +vlib activehdl + +vlib activehdl/xpm +vlib activehdl/blk_mem_gen_v8_4_4 +vlib activehdl/xil_defaultlib + +vmap xpm activehdl/xpm +vmap blk_mem_gen_v8_4_4 activehdl/blk_mem_gen_v8_4_4 +vmap xil_defaultlib activehdl/xil_defaultlib + +vlog -work xpm -sv2k12 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 \ +"../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/file_info.txt new file mode 100644 index 0000000..405a53f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +instr_blk_mem_sim.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/instr_blk_mem_sim.mif b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/instr_blk_mem_sim.mif new file mode 100755 index 0000000..e9bd6fc --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/instr_blk_mem_sim.mif @@ -0,0 +1,396 @@ +0000000000000110000000000000000000000000100010000000000000000000 +0000000000000110000000000000000000000000101100000000000100000000 +0000000000000110000000000000000000000000000000000000000010000000 +0000000000000110000000000000000000000000000100000000000000010000 +0000000000000110000000000000000000000000001000000000000000010000 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+0000000000000000000000000000000000000000000000000000000000000000 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/instr_blk_mem_sim.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/instr_blk_mem_sim.sh new file mode 100755 index 0000000..5c0f525 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/instr_blk_mem_sim.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : instr_blk_mem_sim.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:01 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: instr_blk_mem_sim.sh [-help] +# usage: instr_blk_mem_sim.sh [-lib_map_path] +# usage: instr_blk_mem_sim.sh [-noclean_files] +# usage: instr_blk_mem_sim.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'instr_blk_mem_sim.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "instr_blk_mem_sim.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem_sim.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem_sim.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: instr_blk_mem_sim.sh [-help]\n\ +Usage: instr_blk_mem_sim.sh [-lib_map_path]\n\ +Usage: instr_blk_mem_sim.sh [-reset_run]\n\ +Usage: instr_blk_mem_sim.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/instr_blk_mem_sim.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/instr_blk_mem_sim.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/instr_blk_mem_sim.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/simmem.coe b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/simmem.coe new file mode 100755 index 0000000..90d215f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/simmem.coe @@ -0,0 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\ No newline at end of file diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/simulate.do new file mode 100644 index 0000000..a1d849d --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+instr_blk_mem_sim -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.instr_blk_mem_sim xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {instr_blk_mem_sim.udo} + +run -all + +endsim + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/summary.log new file mode 100755 index 0000000..db51362 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [1024] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [2] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 4.238151 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/README.txt new file mode 100644 index 0000000..3dddba7 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:01 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./instr_blk_mem_sim.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './instr_blk_mem_sim.sh' script. + +./instr_blk_mem_sim.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./instr_blk_mem_sim.sh -noclean_files + +For more information on the script, please type './instr_blk_mem_sim.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/file_info.txt new file mode 100644 index 0000000..405a53f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +instr_blk_mem_sim.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif 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mode 100755 index 0000000..a450636 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/instr_blk_mem_sim.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : instr_blk_mem_sim.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:01 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: instr_blk_mem_sim.sh [-help] +# usage: instr_blk_mem_sim.sh [-lib_map_path] +# usage: instr_blk_mem_sim.sh [-noclean_files] +# usage: instr_blk_mem_sim.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'instr_blk_mem_sim.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "instr_blk_mem_sim.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.instr_blk_mem_sim \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem_sim.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem_sim.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: instr_blk_mem_sim.sh [-help]\n\ +Usage: instr_blk_mem_sim.sh [-lib_map_path]\n\ +Usage: instr_blk_mem_sim.sh [-reset_run]\n\ +Usage: instr_blk_mem_sim.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/run.f b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/run.f new file mode 100644 index 0000000..c8d9ec3 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/run.f @@ -0,0 +1,18 @@ +-makelib ies_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/simmem.coe b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/simmem.coe new file mode 100755 index 0000000..90d215f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/simmem.coe @@ -0,0 +1,398 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0000000000000110000000000000000000000000100010000000000000000000, +0000000000000110000000000000000000000000101100000000000100000000, +0000000000000110000000000000000000000000000000000000000010000000, +0000000000000110000000000000000000000000000100000000000000010000, +0000000000000110000000000000000000000000001000000000000000010000, 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\ No newline at end of file diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/summary.log new file mode 100755 index 0000000..db51362 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [1024] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [2] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 4.238151 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/README.txt new file mode 100644 index 0000000..ce72be2 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:01 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./instr_blk_mem_sim.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './instr_blk_mem_sim.sh' script. + +./instr_blk_mem_sim.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./instr_blk_mem_sim.sh -noclean_files + +For more information on the script, please type './instr_blk_mem_sim.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/compile.do new file mode 100644 index 0000000..0efa779 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/compile.do @@ -0,0 +1,28 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xpm +vlib modelsim_lib/msim/blk_mem_gen_v8_4_4 +vlib modelsim_lib/msim/xil_defaultlib + +vmap xpm modelsim_lib/msim/xpm +vmap blk_mem_gen_v8_4_4 modelsim_lib/msim/blk_mem_gen_v8_4_4 +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xpm -64 -incr -sv \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -64 -incr \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 -incr \ +"../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/file_info.txt new file mode 100644 index 0000000..405a53f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +instr_blk_mem_sim.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/instr_blk_mem_sim.mif b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/instr_blk_mem_sim.mif new file mode 100755 index 0000000..e9bd6fc --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/instr_blk_mem_sim.mif @@ -0,0 +1,396 @@ +0000000000000110000000000000000000000000100010000000000000000000 +0000000000000110000000000000000000000000101100000000000100000000 +0000000000000110000000000000000000000000000000000000000010000000 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+1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001010100000001101 +0000000000000000000000000000000000000000000000000000000000000000 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/instr_blk_mem_sim.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/instr_blk_mem_sim.sh new file mode 100755 index 0000000..d4342a6 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/instr_blk_mem_sim.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : instr_blk_mem_sim.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:01 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: instr_blk_mem_sim.sh [-help] +# usage: instr_blk_mem_sim.sh [-lib_map_path] +# usage: instr_blk_mem_sim.sh [-noclean_files] +# usage: instr_blk_mem_sim.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'instr_blk_mem_sim.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "instr_blk_mem_sim.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem_sim.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/modelsim" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem_sim.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: instr_blk_mem_sim.sh [-help]\n\ +Usage: instr_blk_mem_sim.sh [-lib_map_path]\n\ +Usage: instr_blk_mem_sim.sh [-reset_run]\n\ +Usage: instr_blk_mem_sim.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/instr_blk_mem_sim.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/instr_blk_mem_sim.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/instr_blk_mem_sim.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/simmem.coe b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/simmem.coe new file mode 100755 index 0000000..90d215f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/simmem.coe @@ -0,0 +1,398 @@ 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\ No newline at end of file diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/simulate.do new file mode 100644 index 0000000..782cffc --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.instr_blk_mem_sim xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {instr_blk_mem_sim.udo} + +run -all + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/summary.log new file mode 100755 index 0000000..db51362 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [1024] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [2] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 4.238151 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/README.txt new file mode 100644 index 0000000..ce72be2 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:01 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./instr_blk_mem_sim.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './instr_blk_mem_sim.sh' script. + +./instr_blk_mem_sim.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./instr_blk_mem_sim.sh -noclean_files + +For more information on the script, please type './instr_blk_mem_sim.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/compile.do new file mode 100644 index 0000000..2f2e9ce --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/compile.do @@ -0,0 +1,28 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xpm +vlib questa_lib/msim/blk_mem_gen_v8_4_4 +vlib questa_lib/msim/xil_defaultlib + +vmap xpm questa_lib/msim/xpm +vmap blk_mem_gen_v8_4_4 questa_lib/msim/blk_mem_gen_v8_4_4 +vmap xil_defaultlib questa_lib/msim/xil_defaultlib + +vlog -work xpm -64 -sv \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -64 \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 \ +"../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/elaborate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/elaborate.do new file mode 100644 index 0000000..f4d5ddd --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.instr_blk_mem_sim xil_defaultlib.glbl -o instr_blk_mem_sim_opt diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/file_info.txt new file mode 100644 index 0000000..405a53f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +instr_blk_mem_sim.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git 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file mode 100755 index 0000000..8331cae --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/instr_blk_mem_sim.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : instr_blk_mem_sim.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:01 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: instr_blk_mem_sim.sh [-help] +# usage: instr_blk_mem_sim.sh [-lib_map_path] +# usage: instr_blk_mem_sim.sh [-noclean_files] +# usage: instr_blk_mem_sim.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'instr_blk_mem_sim.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "instr_blk_mem_sim.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem_sim.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem_sim.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: instr_blk_mem_sim.sh [-help]\n\ +Usage: instr_blk_mem_sim.sh [-lib_map_path]\n\ +Usage: instr_blk_mem_sim.sh [-reset_run]\n\ +Usage: instr_blk_mem_sim.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/instr_blk_mem_sim.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/instr_blk_mem_sim.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/instr_blk_mem_sim.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/simmem.coe b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/simmem.coe new file mode 100755 index 0000000..90d215f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/simmem.coe @@ -0,0 +1,398 @@ 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\ No newline at end of file diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/simulate.do new file mode 100644 index 0000000..39a66e5 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib instr_blk_mem_sim_opt + +do {wave.do} + +view wave +view structure +view signals + +do {instr_blk_mem_sim.udo} + +run -all + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/summary.log new file mode 100755 index 0000000..db51362 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [1024] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [2] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 4.238151 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/README.txt new file mode 100644 index 0000000..ce72be2 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:01 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./instr_blk_mem_sim.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './instr_blk_mem_sim.sh' script. + +./instr_blk_mem_sim.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./instr_blk_mem_sim.sh -noclean_files + +For more information on the script, please type './instr_blk_mem_sim.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/compile.do new file mode 100644 index 0000000..d9bed05 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/compile.do @@ -0,0 +1,28 @@ +vlib work +vlib riviera + +vlib riviera/xpm +vlib riviera/blk_mem_gen_v8_4_4 +vlib riviera/xil_defaultlib + +vmap xpm riviera/xpm +vmap blk_mem_gen_v8_4_4 riviera/blk_mem_gen_v8_4_4 +vmap xil_defaultlib riviera/xil_defaultlib + +vlog -work xpm -sv2k12 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 \ +"../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/file_info.txt new file mode 100644 index 0000000..405a53f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +instr_blk_mem_sim.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/instr_blk_mem_sim.mif b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/instr_blk_mem_sim.mif new file mode 100755 index 0000000..e9bd6fc --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/instr_blk_mem_sim.mif @@ -0,0 +1,396 @@ +0000000000000110000000000000000000000000100010000000000000000000 +0000000000000110000000000000000000000000101100000000000100000000 +0000000000000110000000000000000000000000000000000000000010000000 +0000000000000110000000000000000000000000000100000000000000010000 +0000000000000110000000000000000000000000001000000000000000010000 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+0000000000000000000000000000000000000000000000000000000000000000 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/instr_blk_mem_sim.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/instr_blk_mem_sim.sh new file mode 100755 index 0000000..5e32564 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/instr_blk_mem_sim.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : instr_blk_mem_sim.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:01 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: instr_blk_mem_sim.sh [-help] +# usage: instr_blk_mem_sim.sh [-lib_map_path] +# usage: instr_blk_mem_sim.sh [-noclean_files] +# usage: instr_blk_mem_sim.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'instr_blk_mem_sim.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "instr_blk_mem_sim.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem_sim.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem_sim.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: instr_blk_mem_sim.sh [-help]\n\ +Usage: instr_blk_mem_sim.sh [-lib_map_path]\n\ +Usage: instr_blk_mem_sim.sh [-reset_run]\n\ +Usage: instr_blk_mem_sim.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/instr_blk_mem_sim.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/instr_blk_mem_sim.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/instr_blk_mem_sim.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/simmem.coe b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/simmem.coe new file mode 100755 index 0000000..90d215f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/simmem.coe @@ -0,0 +1,398 @@ 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\ No newline at end of file diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/simulate.do new file mode 100644 index 0000000..a1d849d --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+instr_blk_mem_sim -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.instr_blk_mem_sim xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {instr_blk_mem_sim.udo} + +run -all + +endsim + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/summary.log new file mode 100755 index 0000000..db51362 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [1024] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [2] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 4.238151 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/README.txt new file mode 100644 index 0000000..ce72be2 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:01 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./instr_blk_mem_sim.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './instr_blk_mem_sim.sh' script. + +./instr_blk_mem_sim.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./instr_blk_mem_sim.sh -noclean_files + +For more information on the script, please type './instr_blk_mem_sim.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/file_info.txt new file mode 100644 index 0000000..405a53f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +instr_blk_mem_sim.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif 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mode 100755 index 0000000..fab8bfd --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/instr_blk_mem_sim.sh @@ -0,0 +1,235 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : instr_blk_mem_sim.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:01 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: instr_blk_mem_sim.sh [-help] +# usage: instr_blk_mem_sim.sh [-lib_map_path] +# usage: instr_blk_mem_sim.sh [-noclean_files] +# usage: instr_blk_mem_sim.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'instr_blk_mem_sim.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "instr_blk_mem_sim.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + vlogan -work xpm $vlogan_opts -sverilog \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work blk_mem_gen_v8_4_4 $vlogan_opts +v2k \ + "$ref_dir/../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.instr_blk_mem_sim xil_defaultlib.glbl -o instr_blk_mem_sim_simv +} + +# RUN_STEP: <simulate> +simulate() +{ + ./instr_blk_mem_sim_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem_sim.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/vcs" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key instr_blk_mem_sim_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc instr_blk_mem_sim_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem_sim.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: instr_blk_mem_sim.sh [-help]\n\ +Usage: instr_blk_mem_sim.sh [-lib_map_path]\n\ +Usage: instr_blk_mem_sim.sh [-reset_run]\n\ +Usage: instr_blk_mem_sim.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/simmem.coe b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/simmem.coe new file mode 100755 index 0000000..90d215f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/simmem.coe @@ -0,0 +1,398 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0000000000000110000000000000000000000000100010000000000000000000, +0000000000000110000000000000000000000000101100000000000100000000, +0000000000000110000000000000000000000000000000000000000010000000, +0000000000000110000000000000000000000000000100000000000000010000, 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\ No newline at end of file diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/simulate.do new file mode 100644 index 0000000..58afc78 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/summary.log new file mode 100755 index 0000000..db51362 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [1024] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [2] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 4.238151 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/README.txt new file mode 100644 index 0000000..3dddba7 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:01 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./instr_blk_mem_sim.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './instr_blk_mem_sim.sh' script. + +./instr_blk_mem_sim.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./instr_blk_mem_sim.sh -noclean_files + +For more information on the script, please type './instr_blk_mem_sim.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/file_info.txt new file mode 100644 index 0000000..405a53f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +instr_blk_mem_sim.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/instr_blk_mem_sim.mif b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/instr_blk_mem_sim.mif new file mode 100755 index 0000000..e9bd6fc --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/instr_blk_mem_sim.mif @@ -0,0 +1,396 @@ +0000000000000110000000000000000000000000100010000000000000000000 +0000000000000110000000000000000000000000101100000000000100000000 +0000000000000110000000000000000000000000000000000000000010000000 +0000000000000110000000000000000000000000000100000000000000010000 +0000000000000110000000000000000000000000001000000000000000010000 +0001000000000000000000000000000000000000101000000000000000110000 +0100000000000011000000000000000000000000000000000000000000000011 +0001000000000001000000000000000000000000000100000000000000110000 +0100000000000011000000000000000000000000000000000000000000000011 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new file mode 100755 index 0000000..a415fd4 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/instr_blk_mem_sim.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : instr_blk_mem_sim.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:01 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: instr_blk_mem_sim.sh [-help] +# usage: instr_blk_mem_sim.sh [-lib_map_path] +# usage: instr_blk_mem_sim.sh [-noclean_files] +# usage: instr_blk_mem_sim.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'instr_blk_mem_sim.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "instr_blk_mem_sim.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.instr_blk_mem_sim \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem_sim.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem_sim.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: instr_blk_mem_sim.sh [-help]\n\ +Usage: instr_blk_mem_sim.sh [-lib_map_path]\n\ +Usage: instr_blk_mem_sim.sh [-reset_run]\n\ +Usage: instr_blk_mem_sim.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/run.f b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/run.f new file mode 100644 index 0000000..c01da86 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/run.f @@ -0,0 +1,18 @@ +-makelib xcelium_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/simmem.coe b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/simmem.coe new file mode 100755 index 0000000..90d215f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/simmem.coe @@ -0,0 +1,398 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0000000000000110000000000000000000000000100010000000000000000000, +0000000000000110000000000000000000000000101100000000000100000000, +0000000000000110000000000000000000000000000000000000000010000000, +0000000000000110000000000000000000000000000100000000000000010000, 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\ No newline at end of file diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/summary.log new file mode 100755 index 0000000..db51362 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [1024] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [2] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 4.238151 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/README.txt new file mode 100644 index 0000000..ce72be2 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:01 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./instr_blk_mem_sim.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './instr_blk_mem_sim.sh' script. + +./instr_blk_mem_sim.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./instr_blk_mem_sim.sh -noclean_files + +For more information on the script, please type './instr_blk_mem_sim.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/XUPVVH.smi b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/XUPVVH.smi new file mode 100644 index 0000000..7951bb9 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/XUPVVH.smi @@ -0,0 +1,30 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2019.2 (64-bit) --> +<!-- SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 --> +<!-- --> +<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --> +<!-- Nov 6 2019 --> +<!-- --> +<!-- This file is generated by the software with the Tcl write_mem_info command. --> +<!-- Do not edit this file. --> + +<MemInfoSimulation Version="1" Minor="1"> + <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I"> + <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_ADDR_SPACE" ECC="NONE" Begin="0" End="98303"> + <BusBlock> + <BitLane MemType="lmb_bram_I_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303"> + <DataWidth MSB="31" LSB="0"/> + <AddressRange Begin="0" End="16383"/> + <Parity ON="false" NumBits="0"/> + <MemFile Name="bd_9f2c_lmb_bram_I_0.mem"/> + </BitLane> + </BusBlock> + </AddressSpace> + </Processor> + <Config> + <Option Name="Part" Val="xcvu37p-fsvh2892-2-e"/> + </Config> + <DRC> + <Rule Name="RDADDRCHANGE" Val="false"/> + </DRC> +</MemInfoSimulation> diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/cmd.tcl b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/cmd.tcl new file mode 100644 index 0000000..eef7a0f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/file_info.txt new file mode 100644 index 0000000..54dc661 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/file_info.txt @@ -0,0 +1,2 @@ +instr_blk_mem_sim.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/instr_blk_mem_sim.mif b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/instr_blk_mem_sim.mif new file mode 100755 index 0000000..e9bd6fc --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/instr_blk_mem_sim.mif @@ -0,0 +1,396 @@ +0000000000000110000000000000000000000000100010000000000000000000 +0000000000000110000000000000000000000000101100000000000100000000 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automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:01 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: instr_blk_mem_sim.sh [-help] +# usage: instr_blk_mem_sim.sh [-lib_map_path] +# usage: instr_blk_mem_sim.sh [-noclean_files] +# usage: instr_blk_mem_sim.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.2/tps/boost_1_64_0 +xvlog_opts="--relax" + + +# Script info +echo -e "instr_blk_mem_sim.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + xelab --relax --debug typical --mt auto -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot instr_blk_mem_sim xil_defaultlib.instr_blk_mem_sim xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + xsim instr_blk_mem_sim -key {Behavioral:sim_1:Functional:instr_blk_mem_sim} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem_sim.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.2/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb instr_blk_mem_sim.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem_sim.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: instr_blk_mem_sim.sh [-help]\n\ +Usage: instr_blk_mem_sim.sh [-lib_map_path]\n\ +Usage: instr_blk_mem_sim.sh [-reset_run]\n\ +Usage: instr_blk_mem_sim.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/protoinst_files/bd_9f2c.protoinst b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/protoinst_files/bd_9f2c.protoinst new file mode 100644 index 0000000..cf73fce --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/protoinst_files/bd_9f2c.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_9f2c": { + "proto_instances": { + } + } + } +} diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/simmem.coe b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/simmem.coe new file mode 100755 index 0000000..90d215f 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\ No newline at end of file diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/summary.log new file mode 100755 index 0000000..db51362 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [1024] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [2] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 4.238151 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/vlog.prj b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/vlog.prj new file mode 100644 index 0000000..e7fe06f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib \ +"../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/README.txt new file mode 100644 index 0000000..3cd3d87 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +<current_working_directory>/export_sim/<simulator> + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +<simulation_top>.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +<ip-name>.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/activehdl/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/activehdl/README.txt new file mode 100644 index 0000000..838f0e1 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:04 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./phy_ddr4.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './phy_ddr4.sh' script. + +./phy_ddr4.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./phy_ddr4.sh -noclean_files + +For more information on the script, please type './phy_ddr4.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/activehdl/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/activehdl/compile.do new file mode 100644 index 0000000..5d54c15 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/activehdl/compile.do @@ -0,0 +1,124 @@ +vlib work +vlib activehdl + +vlib activehdl/xpm +vlib activehdl/microblaze_v11_0_2 +vlib activehdl/xil_defaultlib +vlib activehdl/lib_cdc_v1_0_2 +vlib activehdl/proc_sys_reset_v5_0_13 +vlib activehdl/lmb_v10_v3_0_10 +vlib activehdl/lmb_bram_if_cntlr_v4_0_17 +vlib activehdl/blk_mem_gen_v8_4_4 +vlib activehdl/iomodule_v3_1_5 + +vmap xpm activehdl/xpm +vmap microblaze_v11_0_2 activehdl/microblaze_v11_0_2 +vmap xil_defaultlib activehdl/xil_defaultlib +vmap lib_cdc_v1_0_2 activehdl/lib_cdc_v1_0_2 +vmap proc_sys_reset_v5_0_13 activehdl/proc_sys_reset_v5_0_13 +vmap lmb_v10_v3_0_10 activehdl/lmb_v10_v3_0_10 +vmap lmb_bram_if_cntlr_v4_0_17 activehdl/lmb_bram_if_cntlr_v4_0_17 +vmap blk_mem_gen_v8_4_4 activehdl/blk_mem_gen_v8_4_4 +vmap iomodule_v3_1_5 activehdl/iomodule_v3_1_5 + +vlog -work xpm -sv2k12 "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vcom -work microblaze_v11_0_2 -93 \ +"../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd" \ + +vcom -work lib_cdc_v1_0_2 -93 \ +"../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \ + +vcom -work proc_sys_reset_v5_0_13 -93 \ +"../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd" \ + +vcom -work lmb_v10_v3_0_10 -93 \ +"../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd" \ + +vcom -work lmb_bram_if_cntlr_v4_0_17 -93 \ +"../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/sim/bd_9f2c_ilmb_cntlr_0.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/sim/bd_9f2c_lmb_bram_I_0.v" \ + +vcom -work xil_defaultlib -93 \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/sim/bd_9f2c_second_dlmb_cntlr_0.vhd" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/sim/bd_9f2c_second_ilmb_cntlr_0.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/sim/bd_9f2c_second_lmb_bram_I_0.v" \ + +vcom -work iomodule_v3_1_5 -93 \ +"../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/sim/bd_9f2c_iomodule_0_0.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/sim/bd_9f2c.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_0/sim/phy_ddr4_microblaze_mcs.v" \ + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/activehdl/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/activehdl/file_info.txt new file mode 100644 index 0000000..1d798bd --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/activehdl/file_info.txt @@ -0,0 +1,61 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_2,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" 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+ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" 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+ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" 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+phy_ddr4_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" 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+microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/activehdl/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/activehdl/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/activehdl/phy_ddr4.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/activehdl/phy_ddr4.sh new file mode 100755 index 0000000..2077f25 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/activehdl/phy_ddr4.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : phy_ddr4.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:04 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: phy_ddr4.sh [-help] +# usage: phy_ddr4.sh [-lib_map_path] +# usage: phy_ddr4.sh [-noclean_files] +# usage: phy_ddr4.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'phy_ddr4.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "phy_ddr4.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: phy_ddr4.sh [-help]\n\ +Usage: phy_ddr4.sh [-lib_map_path]\n\ +Usage: phy_ddr4.sh [-reset_run]\n\ +Usage: phy_ddr4.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/activehdl/phy_ddr4.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/activehdl/phy_ddr4.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/activehdl/phy_ddr4.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/activehdl/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/activehdl/simulate.do new file mode 100644 index 0000000..69f1324 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+phy_ddr4 -L xpm -L microblaze_v11_0_2 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_10 -L lmb_bram_if_cntlr_v4_0_17 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_5 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.phy_ddr4 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {phy_ddr4.udo} + +run -all + +endsim + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/activehdl/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/activehdl/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/ies/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/ies/README.txt new file mode 100644 index 0000000..13253af --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:04 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./phy_ddr4.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './phy_ddr4.sh' script. + +./phy_ddr4.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./phy_ddr4.sh -noclean_files + +For more information on the script, please type './phy_ddr4.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/ies/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/ies/file_info.txt new file mode 100644 index 0000000..0d9fc1a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/ies/file_info.txt @@ -0,0 +1,61 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_2,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +bd_9f2c_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +bd_9f2c_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +lmb_v10_v3_0_vh_rfs.vhd,vhdl,lmb_v10_v3_0_10,../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +bd_9f2c_ilmb_0.vhd,vhdl,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +bd_9f2c_dlmb_0.vhd,vhdl,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,vhdl,lmb_bram_if_cntlr_v4_0_17,../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" 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+ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4_ddr4.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/ies/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/ies/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/ies/phy_ddr4.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/ies/phy_ddr4.sh new file mode 100755 index 0000000..b4560e5 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/ies/phy_ddr4.sh @@ -0,0 +1,181 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : phy_ddr4.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:04 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: phy_ddr4.sh [-help] +# usage: phy_ddr4.sh [-lib_map_path] +# usage: phy_ddr4.sh [-noclean_files] +# usage: phy_ddr4.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'phy_ddr4.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xpm microblaze_v11_0_2 xil_defaultlib lib_cdc_v1_0_2 proc_sys_reset_v5_0_13 lmb_v10_v3_0_10 lmb_bram_if_cntlr_v4_0_17 blk_mem_gen_v8_4_4 iomodule_v3_1_5) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "phy_ddr4.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.phy_ddr4 \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" \ + +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" \ + +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ + +incdir+"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" \ + +incdir+"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" \ + +incdir+"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: phy_ddr4.sh [-help]\n\ +Usage: phy_ddr4.sh [-lib_map_path]\n\ +Usage: phy_ddr4.sh [-reset_run]\n\ +Usage: phy_ddr4.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/ies/run.f b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/ies/run.f new file mode 100644 index 0000000..3f8a560 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/ies/run.f @@ -0,0 +1,102 @@ +-makelib ies_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/microblaze_v11_0_2 \ + "../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd" \ +-endlib +-makelib ies_lib/lib_cdc_v1_0_2 \ + "../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \ +-endlib +-makelib ies_lib/proc_sys_reset_v5_0_13 \ + "../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd" \ +-endlib +-makelib ies_lib/lmb_v10_v3_0_10 \ + "../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd" \ +-endlib +-makelib ies_lib/lmb_bram_if_cntlr_v4_0_17 \ + "../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/sim/bd_9f2c_ilmb_cntlr_0.vhd" \ +-endlib +-makelib ies_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/sim/bd_9f2c_lmb_bram_I_0.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/sim/bd_9f2c_second_dlmb_cntlr_0.vhd" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/sim/bd_9f2c_second_ilmb_cntlr_0.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/sim/bd_9f2c_second_lmb_bram_I_0.v" \ +-endlib +-makelib ies_lib/iomodule_v3_1_5 \ + "../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/sim/bd_9f2c_iomodule_0_0.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/sim/bd_9f2c.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_0/sim/phy_ddr4_microblaze_mcs.v" \ +-endlib +-makelib ies_lib/xil_defaultlib -sv \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/modelsim/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/modelsim/README.txt new file mode 100644 index 0000000..838f0e1 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:04 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./phy_ddr4.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './phy_ddr4.sh' script. + +./phy_ddr4.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./phy_ddr4.sh -noclean_files + +For more information on the script, please type './phy_ddr4.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/modelsim/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/modelsim/compile.do new file mode 100644 index 0000000..e520ac6 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/modelsim/compile.do @@ -0,0 +1,124 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xpm +vlib modelsim_lib/msim/microblaze_v11_0_2 +vlib modelsim_lib/msim/xil_defaultlib +vlib modelsim_lib/msim/lib_cdc_v1_0_2 +vlib modelsim_lib/msim/proc_sys_reset_v5_0_13 +vlib modelsim_lib/msim/lmb_v10_v3_0_10 +vlib modelsim_lib/msim/lmb_bram_if_cntlr_v4_0_17 +vlib modelsim_lib/msim/blk_mem_gen_v8_4_4 +vlib modelsim_lib/msim/iomodule_v3_1_5 + +vmap xpm modelsim_lib/msim/xpm +vmap microblaze_v11_0_2 modelsim_lib/msim/microblaze_v11_0_2 +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib +vmap lib_cdc_v1_0_2 modelsim_lib/msim/lib_cdc_v1_0_2 +vmap proc_sys_reset_v5_0_13 modelsim_lib/msim/proc_sys_reset_v5_0_13 +vmap lmb_v10_v3_0_10 modelsim_lib/msim/lmb_v10_v3_0_10 +vmap lmb_bram_if_cntlr_v4_0_17 modelsim_lib/msim/lmb_bram_if_cntlr_v4_0_17 +vmap blk_mem_gen_v8_4_4 modelsim_lib/msim/blk_mem_gen_v8_4_4 +vmap iomodule_v3_1_5 modelsim_lib/msim/iomodule_v3_1_5 + +vlog -work xpm -64 -incr -sv "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vcom -work microblaze_v11_0_2 -64 -93 \ +"../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd" \ + +vcom -work lib_cdc_v1_0_2 -64 -93 \ +"../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \ + +vcom -work proc_sys_reset_v5_0_13 -64 -93 \ +"../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd" \ + +vcom -work lmb_v10_v3_0_10 -64 -93 \ +"../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd" \ + +vcom -work lmb_bram_if_cntlr_v4_0_17 -64 -93 \ +"../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/sim/bd_9f2c_ilmb_cntlr_0.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -64 -incr "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/sim/bd_9f2c_lmb_bram_I_0.v" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/sim/bd_9f2c_second_dlmb_cntlr_0.vhd" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/sim/bd_9f2c_second_ilmb_cntlr_0.vhd" \ + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/sim/bd_9f2c_second_lmb_bram_I_0.v" \ + +vcom -work iomodule_v3_1_5 -64 -93 \ +"../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/sim/bd_9f2c_iomodule_0_0.vhd" \ + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/sim/bd_9f2c.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_0/sim/phy_ddr4_microblaze_mcs.v" \ + +vlog -work xil_defaultlib -64 -incr -sv "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/modelsim/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/modelsim/file_info.txt new file mode 100644 index 0000000..1d798bd --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/modelsim/file_info.txt @@ -0,0 +1,61 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_2,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +bd_9f2c_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +bd_9f2c_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +lmb_v10_v3_0_vh_rfs.vhd,vhdl,lmb_v10_v3_0_10,../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +bd_9f2c_ilmb_0.vhd,vhdl,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +bd_9f2c_dlmb_0.vhd,vhdl,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,vhdl,lmb_bram_if_cntlr_v4_0_17,../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +bd_9f2c_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +bd_9f2c_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/sim/bd_9f2c_ilmb_cntlr_0.vhd,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" 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+ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4_ddr4.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/modelsim/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/modelsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/modelsim/phy_ddr4.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/modelsim/phy_ddr4.sh new file mode 100755 index 0000000..d819e6d --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/modelsim/phy_ddr4.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : phy_ddr4.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:04 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: phy_ddr4.sh [-help] +# usage: phy_ddr4.sh [-lib_map_path] +# usage: phy_ddr4.sh [-noclean_files] +# usage: phy_ddr4.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'phy_ddr4.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "phy_ddr4.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/modelsim" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: phy_ddr4.sh [-help]\n\ +Usage: phy_ddr4.sh [-lib_map_path]\n\ +Usage: phy_ddr4.sh [-reset_run]\n\ +Usage: phy_ddr4.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/modelsim/phy_ddr4.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/modelsim/phy_ddr4.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/modelsim/phy_ddr4.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/modelsim/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/modelsim/simulate.do new file mode 100644 index 0000000..4674856 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xpm -L microblaze_v11_0_2 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_10 -L lmb_bram_if_cntlr_v4_0_17 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_5 -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.phy_ddr4 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {phy_ddr4.udo} + +run -all + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/modelsim/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/modelsim/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/questa/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/questa/README.txt new file mode 100644 index 0000000..838f0e1 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:04 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./phy_ddr4.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './phy_ddr4.sh' script. + +./phy_ddr4.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./phy_ddr4.sh -noclean_files + +For more information on the script, please type './phy_ddr4.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/questa/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/questa/compile.do new file mode 100644 index 0000000..3c8edfa --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/questa/compile.do @@ -0,0 +1,124 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xpm +vlib questa_lib/msim/microblaze_v11_0_2 +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/lib_cdc_v1_0_2 +vlib questa_lib/msim/proc_sys_reset_v5_0_13 +vlib questa_lib/msim/lmb_v10_v3_0_10 +vlib questa_lib/msim/lmb_bram_if_cntlr_v4_0_17 +vlib questa_lib/msim/blk_mem_gen_v8_4_4 +vlib questa_lib/msim/iomodule_v3_1_5 + +vmap xpm questa_lib/msim/xpm +vmap microblaze_v11_0_2 questa_lib/msim/microblaze_v11_0_2 +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap lib_cdc_v1_0_2 questa_lib/msim/lib_cdc_v1_0_2 +vmap proc_sys_reset_v5_0_13 questa_lib/msim/proc_sys_reset_v5_0_13 +vmap lmb_v10_v3_0_10 questa_lib/msim/lmb_v10_v3_0_10 +vmap lmb_bram_if_cntlr_v4_0_17 questa_lib/msim/lmb_bram_if_cntlr_v4_0_17 +vmap blk_mem_gen_v8_4_4 questa_lib/msim/blk_mem_gen_v8_4_4 +vmap iomodule_v3_1_5 questa_lib/msim/iomodule_v3_1_5 + +vlog -work xpm -64 -sv "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vcom -work microblaze_v11_0_2 -64 -93 \ +"../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd" \ + +vcom -work lib_cdc_v1_0_2 -64 -93 \ +"../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \ + +vcom -work proc_sys_reset_v5_0_13 -64 -93 \ +"../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd" \ + +vcom -work lmb_v10_v3_0_10 -64 -93 \ +"../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd" \ + +vcom -work lmb_bram_if_cntlr_v4_0_17 -64 -93 \ +"../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/sim/bd_9f2c_ilmb_cntlr_0.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -64 "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/sim/bd_9f2c_lmb_bram_I_0.v" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/sim/bd_9f2c_second_dlmb_cntlr_0.vhd" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/sim/bd_9f2c_second_ilmb_cntlr_0.vhd" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/sim/bd_9f2c_second_lmb_bram_I_0.v" \ + +vcom -work iomodule_v3_1_5 -64 -93 \ +"../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/sim/bd_9f2c_iomodule_0_0.vhd" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/sim/bd_9f2c.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_0/sim/phy_ddr4_microblaze_mcs.v" \ + +vlog -work xil_defaultlib -64 -sv "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/questa/elaborate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/questa/elaborate.do new file mode 100644 index 0000000..9d0b70d --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xpm -L microblaze_v11_0_2 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_10 -L lmb_bram_if_cntlr_v4_0_17 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_5 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.phy_ddr4 xil_defaultlib.glbl -o phy_ddr4_opt diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/questa/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/questa/file_info.txt new file mode 100644 index 0000000..1d798bd --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/questa/file_info.txt @@ -0,0 +1,61 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_2,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +bd_9f2c_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +bd_9f2c_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +lmb_v10_v3_0_vh_rfs.vhd,vhdl,lmb_v10_v3_0_10,../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" 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+bd_9f2c_dlmb_0.vhd,vhdl,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" 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+ddr4_v2_2_cal_sync.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4_ddr4.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/questa/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/questa/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/questa/phy_ddr4.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/questa/phy_ddr4.sh new file mode 100755 index 0000000..efae005 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/questa/phy_ddr4.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : phy_ddr4.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:04 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: phy_ddr4.sh [-help] +# usage: phy_ddr4.sh [-lib_map_path] +# usage: phy_ddr4.sh [-noclean_files] +# usage: phy_ddr4.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'phy_ddr4.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "phy_ddr4.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: phy_ddr4.sh [-help]\n\ +Usage: phy_ddr4.sh [-lib_map_path]\n\ +Usage: phy_ddr4.sh [-reset_run]\n\ +Usage: phy_ddr4.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/questa/phy_ddr4.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/questa/phy_ddr4.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/questa/phy_ddr4.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/questa/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/questa/simulate.do new file mode 100644 index 0000000..1d07864 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib phy_ddr4_opt + +do {wave.do} + +view wave +view structure +view signals + +do {phy_ddr4.udo} + +run -all + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/questa/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/questa/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/riviera/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/riviera/README.txt new file mode 100644 index 0000000..838f0e1 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:04 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./phy_ddr4.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './phy_ddr4.sh' script. + +./phy_ddr4.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./phy_ddr4.sh -noclean_files + +For more information on the script, please type './phy_ddr4.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/riviera/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/riviera/compile.do new file mode 100644 index 0000000..e932984 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/riviera/compile.do @@ -0,0 +1,124 @@ +vlib work +vlib riviera + +vlib riviera/xpm +vlib riviera/microblaze_v11_0_2 +vlib riviera/xil_defaultlib +vlib riviera/lib_cdc_v1_0_2 +vlib riviera/proc_sys_reset_v5_0_13 +vlib riviera/lmb_v10_v3_0_10 +vlib riviera/lmb_bram_if_cntlr_v4_0_17 +vlib riviera/blk_mem_gen_v8_4_4 +vlib riviera/iomodule_v3_1_5 + +vmap xpm riviera/xpm +vmap microblaze_v11_0_2 riviera/microblaze_v11_0_2 +vmap xil_defaultlib riviera/xil_defaultlib +vmap lib_cdc_v1_0_2 riviera/lib_cdc_v1_0_2 +vmap proc_sys_reset_v5_0_13 riviera/proc_sys_reset_v5_0_13 +vmap lmb_v10_v3_0_10 riviera/lmb_v10_v3_0_10 +vmap lmb_bram_if_cntlr_v4_0_17 riviera/lmb_bram_if_cntlr_v4_0_17 +vmap blk_mem_gen_v8_4_4 riviera/blk_mem_gen_v8_4_4 +vmap iomodule_v3_1_5 riviera/iomodule_v3_1_5 + +vlog -work xpm -sv2k12 "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vcom -work microblaze_v11_0_2 -93 \ +"../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd" \ + +vcom -work lib_cdc_v1_0_2 -93 \ +"../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \ + +vcom -work proc_sys_reset_v5_0_13 -93 \ +"../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd" \ + +vcom -work lmb_v10_v3_0_10 -93 \ +"../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd" \ + +vcom -work lmb_bram_if_cntlr_v4_0_17 -93 \ +"../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/sim/bd_9f2c_ilmb_cntlr_0.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/sim/bd_9f2c_lmb_bram_I_0.v" \ + +vcom -work xil_defaultlib -93 \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/sim/bd_9f2c_second_dlmb_cntlr_0.vhd" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/sim/bd_9f2c_second_ilmb_cntlr_0.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/sim/bd_9f2c_second_lmb_bram_I_0.v" \ + +vcom -work iomodule_v3_1_5 -93 \ +"../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/sim/bd_9f2c_iomodule_0_0.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/sim/bd_9f2c.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_0/sim/phy_ddr4_microblaze_mcs.v" \ + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/riviera/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/riviera/file_info.txt new file mode 100644 index 0000000..1d798bd --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/riviera/file_info.txt @@ -0,0 +1,61 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_2,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" 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+ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" 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+microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/riviera/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/riviera/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4.sh new file mode 100755 index 0000000..2966464 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : phy_ddr4.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:04 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: phy_ddr4.sh [-help] +# usage: phy_ddr4.sh [-lib_map_path] +# usage: phy_ddr4.sh [-noclean_files] +# usage: phy_ddr4.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'phy_ddr4.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "phy_ddr4.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: phy_ddr4.sh [-help]\n\ +Usage: phy_ddr4.sh [-lib_map_path]\n\ +Usage: phy_ddr4.sh [-reset_run]\n\ +Usage: phy_ddr4.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/riviera/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/riviera/simulate.do new file mode 100644 index 0000000..69f1324 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+phy_ddr4 -L xpm -L microblaze_v11_0_2 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_10 -L lmb_bram_if_cntlr_v4_0_17 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_5 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.phy_ddr4 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {phy_ddr4.udo} + +run -all + +endsim + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/riviera/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/riviera/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/vcs/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/vcs/README.txt new file mode 100644 index 0000000..838f0e1 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:04 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./phy_ddr4.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './phy_ddr4.sh' script. + +./phy_ddr4.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./phy_ddr4.sh -noclean_files + +For more information on the script, please type './phy_ddr4.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/vcs/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/vcs/file_info.txt new file mode 100644 index 0000000..0d9fc1a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/vcs/file_info.txt @@ -0,0 +1,61 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_2,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +bd_9f2c_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +bd_9f2c_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +lmb_v10_v3_0_vh_rfs.vhd,vhdl,lmb_v10_v3_0_10,../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +bd_9f2c_ilmb_0.vhd,vhdl,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +bd_9f2c_dlmb_0.vhd,vhdl,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,vhdl,lmb_bram_if_cntlr_v4_0_17,../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" 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+ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4_ddr4.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/vcs/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/vcs/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/vcs/phy_ddr4.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/vcs/phy_ddr4.sh new file mode 100755 index 0000000..05b23ff --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/vcs/phy_ddr4.sh @@ -0,0 +1,334 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : phy_ddr4.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:04 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: phy_ddr4.sh [-help] +# usage: phy_ddr4.sh [-lib_map_path] +# usage: phy_ddr4.sh [-noclean_files] +# usage: phy_ddr4.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'phy_ddr4.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xpm microblaze_v11_0_2 xil_defaultlib lib_cdc_v1_0_2 proc_sys_reset_v5_0_13 lmb_v10_v3_0_10 lmb_bram_if_cntlr_v4_0_17 blk_mem_gen_v8_4_4 iomodule_v3_1_5) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "phy_ddr4.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + vlogan -work xpm $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work microblaze_v11_0_2 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work xil_defaultlib $vhdlan_opts \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work lib_cdc_v1_0_2 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work proc_sys_reset_v5_0_13 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work xil_defaultlib $vhdlan_opts \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work lmb_v10_v3_0_10 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work xil_defaultlib $vhdlan_opts \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work lmb_bram_if_cntlr_v4_0_17 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work xil_defaultlib $vhdlan_opts \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/sim/bd_9f2c_ilmb_cntlr_0.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work blk_mem_gen_v8_4_4 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ + "$ref_dir/../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/sim/bd_9f2c_lmb_bram_I_0.v" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xil_defaultlib $vhdlan_opts \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/sim/bd_9f2c_second_dlmb_cntlr_0.vhd" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/sim/bd_9f2c_second_ilmb_cntlr_0.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/sim/bd_9f2c_second_lmb_bram_I_0.v" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work iomodule_v3_1_5 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work xil_defaultlib $vhdlan_opts \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/sim/bd_9f2c_iomodule_0_0.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/sim/bd_9f2c.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_0/sim/phy_ddr4_microblaze_mcs.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xil_defaultlib $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.phy_ddr4 xil_defaultlib.glbl -o phy_ddr4_simv +} + +# RUN_STEP: <simulate> +simulate() +{ + ./phy_ddr4_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/vcs" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key phy_ddr4_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc phy_ddr4_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: phy_ddr4.sh [-help]\n\ +Usage: phy_ddr4.sh [-lib_map_path]\n\ +Usage: phy_ddr4.sh [-reset_run]\n\ +Usage: phy_ddr4.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/vcs/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/vcs/simulate.do new file mode 100644 index 0000000..58afc78 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xcelium/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xcelium/README.txt new file mode 100644 index 0000000..13253af --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:04 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./phy_ddr4.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './phy_ddr4.sh' script. + +./phy_ddr4.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./phy_ddr4.sh -noclean_files + +For more information on the script, please type './phy_ddr4.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xcelium/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xcelium/file_info.txt new file mode 100644 index 0000000..0d9fc1a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xcelium/file_info.txt @@ -0,0 +1,61 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_2,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" 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+phy_ddr4_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xcelium/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xcelium/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xcelium/phy_ddr4.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xcelium/phy_ddr4.sh new file mode 100755 index 0000000..0851d7d --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xcelium/phy_ddr4.sh @@ -0,0 +1,181 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : phy_ddr4.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:04 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: phy_ddr4.sh [-help] +# usage: phy_ddr4.sh [-lib_map_path] +# usage: phy_ddr4.sh [-noclean_files] +# usage: phy_ddr4.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'phy_ddr4.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xpm microblaze_v11_0_2 xil_defaultlib lib_cdc_v1_0_2 proc_sys_reset_v5_0_13 lmb_v10_v3_0_10 lmb_bram_if_cntlr_v4_0_17 blk_mem_gen_v8_4_4 iomodule_v3_1_5) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "phy_ddr4.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.phy_ddr4 \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" \ + +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" \ + +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ + +incdir+"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" \ + +incdir+"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" \ + +incdir+"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: phy_ddr4.sh [-help]\n\ +Usage: phy_ddr4.sh [-lib_map_path]\n\ +Usage: phy_ddr4.sh [-reset_run]\n\ +Usage: phy_ddr4.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xcelium/run.f b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xcelium/run.f new file mode 100644 index 0000000..3494810 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xcelium/run.f @@ -0,0 +1,102 @@ +-makelib xcelium_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/microblaze_v11_0_2 \ + "../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd" \ +-endlib +-makelib xcelium_lib/lib_cdc_v1_0_2 \ + "../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \ +-endlib +-makelib xcelium_lib/proc_sys_reset_v5_0_13 \ + "../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd" \ +-endlib +-makelib xcelium_lib/lmb_v10_v3_0_10 \ + "../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd" \ +-endlib +-makelib xcelium_lib/lmb_bram_if_cntlr_v4_0_17 \ + "../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/sim/bd_9f2c_ilmb_cntlr_0.vhd" \ +-endlib +-makelib xcelium_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/sim/bd_9f2c_lmb_bram_I_0.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/sim/bd_9f2c_second_dlmb_cntlr_0.vhd" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/sim/bd_9f2c_second_ilmb_cntlr_0.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/sim/bd_9f2c_second_lmb_bram_I_0.v" \ +-endlib +-makelib xcelium_lib/iomodule_v3_1_5 \ + "../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/sim/bd_9f2c_iomodule_0_0.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/sim/bd_9f2c.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_0/sim/phy_ddr4_microblaze_mcs.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib -sv \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xsim/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xsim/README.txt new file mode 100644 index 0000000..838f0e1 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:04 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./phy_ddr4.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './phy_ddr4.sh' script. + +./phy_ddr4.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./phy_ddr4.sh -noclean_files + +For more information on the script, please type './phy_ddr4.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xsim/XUPVVH.smi b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xsim/XUPVVH.smi new file mode 100644 index 0000000..7951bb9 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xsim/XUPVVH.smi @@ -0,0 +1,30 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2019.2 (64-bit) --> +<!-- SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 --> +<!-- --> +<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --> +<!-- Nov 6 2019 --> +<!-- --> +<!-- This file is generated by the software with the Tcl write_mem_info command. --> +<!-- Do not edit this file. --> + +<MemInfoSimulation Version="1" Minor="1"> + <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I"> + <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_ADDR_SPACE" ECC="NONE" Begin="0" End="98303"> + <BusBlock> + <BitLane MemType="lmb_bram_I_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303"> + <DataWidth MSB="31" LSB="0"/> + <AddressRange Begin="0" End="16383"/> + <Parity ON="false" NumBits="0"/> + <MemFile Name="bd_9f2c_lmb_bram_I_0.mem"/> + </BitLane> + </BusBlock> + </AddressSpace> + </Processor> + <Config> + <Option Name="Part" Val="xcvu37p-fsvh2892-2-e"/> + </Config> + <DRC> + <Rule Name="RDADDRCHANGE" Val="false"/> + </DRC> +</MemInfoSimulation> diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xsim/cmd.tcl b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xsim/cmd.tcl new file mode 100644 index 0000000..eef7a0f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xsim/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xsim/file_info.txt new file mode 100644 index 0000000..43d214f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xsim/file_info.txt @@ -0,0 +1,50 @@ +bd_9f2c_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +bd_9f2c_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +bd_9f2c_ilmb_0.vhd,vhdl,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +bd_9f2c_dlmb_0.vhd,vhdl,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +bd_9f2c_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" 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+phy_ddr4_phy.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_infrastructure.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_xsdb_bram.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_write.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_wr_byte.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_wr_bit.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_sync.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4_ddr4.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xsim/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xsim/phy_ddr4.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xsim/phy_ddr4.sh new file mode 100755 index 0000000..5236476 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xsim/phy_ddr4.sh @@ -0,0 +1,214 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : phy_ddr4.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:04 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: phy_ddr4.sh [-help] +# usage: phy_ddr4.sh [-lib_map_path] +# usage: phy_ddr4.sh [-noclean_files] +# usage: phy_ddr4.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.2/tps/boost_1_64_0 +xvlog_opts="--relax" +xvhdl_opts="--relax" + + +# Script info +echo -e "phy_ddr4.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + xvhdl $xvhdl_opts -prj vhdl.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + xelab --relax --debug typical --mt auto -L microblaze_v11_0_2 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_10 -L lmb_bram_if_cntlr_v4_0_17 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_5 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot phy_ddr4 xil_defaultlib.phy_ddr4 xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + xsim phy_ddr4 -key {Behavioral:sim_1:Functional:phy_ddr4} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.2/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb phy_ddr4.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: phy_ddr4.sh [-help]\n\ +Usage: phy_ddr4.sh [-lib_map_path]\n\ +Usage: phy_ddr4.sh [-reset_run]\n\ +Usage: phy_ddr4.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xsim/protoinst_files/bd_9f2c.protoinst b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xsim/protoinst_files/bd_9f2c.protoinst new file mode 100644 index 0000000..cf73fce --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xsim/protoinst_files/bd_9f2c.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_9f2c": { + "proto_instances": { + } + } + } +} diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xsim/vhdl.prj b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xsim/vhdl.prj new file mode 100644 index 0000000..6148fd8 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xsim/vhdl.prj @@ -0,0 +1,12 @@ +vhdl xil_defaultlib \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/sim/bd_9f2c_ilmb_cntlr_0.vhd" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/sim/bd_9f2c_second_dlmb_cntlr_0.vhd" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/sim/bd_9f2c_second_ilmb_cntlr_0.vhd" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/sim/bd_9f2c_iomodule_0_0.vhd" \ + +nosort diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xsim/vlog.prj b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xsim/vlog.prj new file mode 100644 index 0000000..8ab6c6c --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/xsim/vlog.prj @@ -0,0 +1,47 @@ +verilog xil_defaultlib --include "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" --include "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" --include "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/sim/bd_9f2c_lmb_bram_I_0.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/sim/bd_9f2c_second_lmb_bram_I_0.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/sim/bd_9f2c.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_0/sim/phy_ddr4_microblaze_mcs.v" \ + +sv xil_defaultlib --include "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" --include "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" --include "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/README.txt new file mode 100644 index 0000000..3cd3d87 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +<current_working_directory>/export_sim/<simulator> + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +<simulation_top>.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +<ip-name>.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/activehdl/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/activehdl/README.txt new file mode 100644 index 0000000..1c80f61 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:10 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./pr_read_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './pr_read_mem.sh' script. + +./pr_read_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./pr_read_mem.sh -noclean_files + +For more information on the script, please type './pr_read_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/activehdl/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/activehdl/compile.do new file mode 100644 index 0000000..948752b --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/activehdl/compile.do @@ -0,0 +1,28 @@ +vlib work +vlib activehdl + +vlib activehdl/xpm +vlib activehdl/blk_mem_gen_v8_4_4 +vlib activehdl/xil_defaultlib + +vmap xpm activehdl/xpm +vmap blk_mem_gen_v8_4_4 activehdl/blk_mem_gen_v8_4_4 +vmap xil_defaultlib activehdl/xil_defaultlib + +vlog -work xpm -sv2k12 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 \ +"../../../../XUPVVH.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/activehdl/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/activehdl/file_info.txt new file mode 100644 index 0000000..fc38872 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/activehdl/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +pr_read_mem.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/activehdl/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/activehdl/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read.coe b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read.coe new file mode 100755 index 0000000..b9ccb93 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read.coe @@ -0,0 +1,15 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010000000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001011000001100101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001001000001000101, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read_mem.mif b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read_mem.mif new file mode 100755 index 0000000..ef3787e --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read_mem.mif @@ -0,0 +1,13 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010000000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001011000001100101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001001000001000101 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read_mem.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read_mem.sh new file mode 100755 index 0000000..4e1c2d8 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read_mem.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : pr_read_mem.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:10 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: pr_read_mem.sh [-help] +# usage: pr_read_mem.sh [-lib_map_path] +# usage: pr_read_mem.sh [-noclean_files] +# usage: pr_read_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'pr_read_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "pr_read_mem.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./pr_read_mem.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./pr_read_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: pr_read_mem.sh [-help]\n\ +Usage: pr_read_mem.sh [-lib_map_path]\n\ +Usage: pr_read_mem.sh [-reset_run]\n\ +Usage: pr_read_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read_mem.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read_mem.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read_mem.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/activehdl/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/activehdl/simulate.do new file mode 100644 index 0000000..c1ce05c --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+pr_read_mem -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.pr_read_mem xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {pr_read_mem.udo} + +run -all + +endsim + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/activehdl/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/activehdl/summary.log new file mode 100755 index 0000000..abd7c4a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/activehdl/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [16] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/activehdl/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/activehdl/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/ies/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/ies/README.txt new file mode 100644 index 0000000..6e10a2a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:10 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./pr_read_mem.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './pr_read_mem.sh' script. + +./pr_read_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./pr_read_mem.sh -noclean_files + +For more information on the script, please type './pr_read_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/ies/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/ies/file_info.txt new file mode 100644 index 0000000..fc38872 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/ies/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +pr_read_mem.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/ies/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/ies/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/ies/pr_read.coe b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/ies/pr_read.coe new file mode 100755 index 0000000..b9ccb93 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/ies/pr_read.coe @@ -0,0 +1,15 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010000000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001011000001100101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001001000001000101, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/ies/pr_read_mem.mif b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/ies/pr_read_mem.mif new file mode 100755 index 0000000..ef3787e --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/ies/pr_read_mem.mif @@ -0,0 +1,13 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010000000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001011000001100101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001001000001000101 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/ies/pr_read_mem.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/ies/pr_read_mem.sh new file mode 100755 index 0000000..c5c62cb --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/ies/pr_read_mem.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : pr_read_mem.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:10 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: pr_read_mem.sh [-help] +# usage: pr_read_mem.sh [-lib_map_path] +# usage: pr_read_mem.sh [-noclean_files] +# usage: pr_read_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'pr_read_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "pr_read_mem.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.pr_read_mem \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./pr_read_mem.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./pr_read_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: pr_read_mem.sh [-help]\n\ +Usage: pr_read_mem.sh [-lib_map_path]\n\ +Usage: pr_read_mem.sh [-reset_run]\n\ +Usage: pr_read_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/ies/run.f b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/ies/run.f new file mode 100644 index 0000000..aaedb7d --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/ies/run.f @@ -0,0 +1,18 @@ +-makelib ies_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/ies/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/ies/summary.log new file mode 100755 index 0000000..abd7c4a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/ies/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [16] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/modelsim/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/modelsim/README.txt new file mode 100644 index 0000000..1c80f61 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:10 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./pr_read_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './pr_read_mem.sh' script. + +./pr_read_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./pr_read_mem.sh -noclean_files + +For more information on the script, please type './pr_read_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/modelsim/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/modelsim/compile.do new file mode 100644 index 0000000..bdbfdb4 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/modelsim/compile.do @@ -0,0 +1,28 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xpm +vlib modelsim_lib/msim/blk_mem_gen_v8_4_4 +vlib modelsim_lib/msim/xil_defaultlib + +vmap xpm modelsim_lib/msim/xpm +vmap blk_mem_gen_v8_4_4 modelsim_lib/msim/blk_mem_gen_v8_4_4 +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xpm -64 -incr -sv \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -64 -incr \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 -incr \ +"../../../../XUPVVH.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/modelsim/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/modelsim/file_info.txt new file mode 100644 index 0000000..fc38872 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/modelsim/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +pr_read_mem.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/modelsim/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/modelsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read.coe b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read.coe new file mode 100755 index 0000000..b9ccb93 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read.coe @@ -0,0 +1,15 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010000000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001011000001100101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001001000001000101, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read_mem.mif b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read_mem.mif new file mode 100755 index 0000000..ef3787e --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read_mem.mif @@ -0,0 +1,13 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010000000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001011000001100101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001001000001000101 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read_mem.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read_mem.sh new file mode 100755 index 0000000..9036dd0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read_mem.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : pr_read_mem.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:10 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: pr_read_mem.sh [-help] +# usage: pr_read_mem.sh [-lib_map_path] +# usage: pr_read_mem.sh [-noclean_files] +# usage: pr_read_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'pr_read_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "pr_read_mem.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./pr_read_mem.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/modelsim" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./pr_read_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: pr_read_mem.sh [-help]\n\ +Usage: pr_read_mem.sh [-lib_map_path]\n\ +Usage: pr_read_mem.sh [-reset_run]\n\ +Usage: pr_read_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read_mem.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read_mem.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read_mem.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/modelsim/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/modelsim/simulate.do new file mode 100644 index 0000000..862fd00 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.pr_read_mem xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {pr_read_mem.udo} + +run -all + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/modelsim/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/modelsim/summary.log new file mode 100755 index 0000000..abd7c4a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/modelsim/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [16] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/modelsim/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/modelsim/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/README.txt new file mode 100644 index 0000000..1c80f61 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:10 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./pr_read_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './pr_read_mem.sh' script. + +./pr_read_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./pr_read_mem.sh -noclean_files + +For more information on the script, please type './pr_read_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/compile.do new file mode 100644 index 0000000..e8d03b1 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/compile.do @@ -0,0 +1,28 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xpm +vlib questa_lib/msim/blk_mem_gen_v8_4_4 +vlib questa_lib/msim/xil_defaultlib + +vmap xpm questa_lib/msim/xpm +vmap blk_mem_gen_v8_4_4 questa_lib/msim/blk_mem_gen_v8_4_4 +vmap xil_defaultlib questa_lib/msim/xil_defaultlib + +vlog -work xpm -64 -sv \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -64 \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 \ +"../../../../XUPVVH.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/elaborate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/elaborate.do new file mode 100644 index 0000000..8f94b7d --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.pr_read_mem xil_defaultlib.glbl -o pr_read_mem_opt diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/file_info.txt new file mode 100644 index 0000000..fc38872 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +pr_read_mem.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read.coe b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read.coe new file mode 100755 index 0000000..b9ccb93 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read.coe @@ -0,0 +1,15 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010000000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001011000001100101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001001000001000101, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read_mem.mif b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read_mem.mif new file mode 100755 index 0000000..ef3787e --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read_mem.mif @@ -0,0 +1,13 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010000000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001011000001100101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001001000001000101 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read_mem.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read_mem.sh new file mode 100755 index 0000000..c87b537 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read_mem.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : pr_read_mem.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:10 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: pr_read_mem.sh [-help] +# usage: pr_read_mem.sh [-lib_map_path] +# usage: pr_read_mem.sh [-noclean_files] +# usage: pr_read_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'pr_read_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "pr_read_mem.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./pr_read_mem.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./pr_read_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: pr_read_mem.sh [-help]\n\ +Usage: pr_read_mem.sh [-lib_map_path]\n\ +Usage: pr_read_mem.sh [-reset_run]\n\ +Usage: pr_read_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read_mem.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read_mem.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read_mem.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/simulate.do new file mode 100644 index 0000000..8d9a32a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib pr_read_mem_opt + +do {wave.do} + +view wave +view structure +view signals + +do {pr_read_mem.udo} + +run -all + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/summary.log new file mode 100755 index 0000000..abd7c4a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [16] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/riviera/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/riviera/README.txt new file mode 100644 index 0000000..1c80f61 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:10 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./pr_read_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './pr_read_mem.sh' script. + +./pr_read_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./pr_read_mem.sh -noclean_files + +For more information on the script, please type './pr_read_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/riviera/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/riviera/compile.do new file mode 100644 index 0000000..9489577 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/riviera/compile.do @@ -0,0 +1,28 @@ +vlib work +vlib riviera + +vlib riviera/xpm +vlib riviera/blk_mem_gen_v8_4_4 +vlib riviera/xil_defaultlib + +vmap xpm riviera/xpm +vmap blk_mem_gen_v8_4_4 riviera/blk_mem_gen_v8_4_4 +vmap xil_defaultlib riviera/xil_defaultlib + +vlog -work xpm -sv2k12 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 \ +"../../../../XUPVVH.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/riviera/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/riviera/file_info.txt new file mode 100644 index 0000000..fc38872 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/riviera/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +pr_read_mem.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/riviera/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/riviera/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read.coe b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read.coe new file mode 100755 index 0000000..b9ccb93 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read.coe @@ -0,0 +1,15 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010000000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001011000001100101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001001000001000101, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read_mem.mif b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read_mem.mif new file mode 100755 index 0000000..ef3787e --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read_mem.mif @@ -0,0 +1,13 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010000000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001011000001100101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001001000001000101 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read_mem.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read_mem.sh new file mode 100755 index 0000000..94222ab --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read_mem.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : pr_read_mem.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:10 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: pr_read_mem.sh [-help] +# usage: pr_read_mem.sh [-lib_map_path] +# usage: pr_read_mem.sh [-noclean_files] +# usage: pr_read_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'pr_read_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "pr_read_mem.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./pr_read_mem.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./pr_read_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: pr_read_mem.sh [-help]\n\ +Usage: pr_read_mem.sh [-lib_map_path]\n\ +Usage: pr_read_mem.sh [-reset_run]\n\ +Usage: pr_read_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read_mem.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read_mem.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read_mem.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/riviera/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/riviera/simulate.do new file mode 100644 index 0000000..c1ce05c --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+pr_read_mem -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.pr_read_mem xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {pr_read_mem.udo} + +run -all + +endsim + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/riviera/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/riviera/summary.log new file mode 100755 index 0000000..abd7c4a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/riviera/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [16] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/riviera/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/riviera/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/vcs/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/vcs/README.txt new file mode 100644 index 0000000..1c80f61 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:10 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./pr_read_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './pr_read_mem.sh' script. + +./pr_read_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./pr_read_mem.sh -noclean_files + +For more information on the script, please type './pr_read_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/vcs/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/vcs/file_info.txt new file mode 100644 index 0000000..fc38872 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/vcs/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +pr_read_mem.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/vcs/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/vcs/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/vcs/pr_read.coe b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/vcs/pr_read.coe new file mode 100755 index 0000000..b9ccb93 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/vcs/pr_read.coe @@ -0,0 +1,15 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010000000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001011000001100101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001001000001000101, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/vcs/pr_read_mem.mif b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/vcs/pr_read_mem.mif new file mode 100755 index 0000000..ef3787e --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/vcs/pr_read_mem.mif @@ -0,0 +1,13 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010000000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001011000001100101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001001000001000101 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/vcs/pr_read_mem.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/vcs/pr_read_mem.sh new file mode 100755 index 0000000..f3b4b9e --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/vcs/pr_read_mem.sh @@ -0,0 +1,235 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : pr_read_mem.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:10 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: pr_read_mem.sh [-help] +# usage: pr_read_mem.sh [-lib_map_path] +# usage: pr_read_mem.sh [-noclean_files] +# usage: pr_read_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'pr_read_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "pr_read_mem.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + vlogan -work xpm $vlogan_opts -sverilog \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work blk_mem_gen_v8_4_4 $vlogan_opts +v2k \ + "$ref_dir/../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.pr_read_mem xil_defaultlib.glbl -o pr_read_mem_simv +} + +# RUN_STEP: <simulate> +simulate() +{ + ./pr_read_mem_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./pr_read_mem.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/vcs" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key pr_read_mem_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc pr_read_mem_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./pr_read_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: pr_read_mem.sh [-help]\n\ +Usage: pr_read_mem.sh [-lib_map_path]\n\ +Usage: pr_read_mem.sh [-reset_run]\n\ +Usage: pr_read_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/vcs/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/vcs/simulate.do new file mode 100644 index 0000000..58afc78 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/vcs/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/vcs/summary.log new file mode 100755 index 0000000..abd7c4a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/vcs/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [16] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xcelium/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xcelium/README.txt new file mode 100644 index 0000000..6e10a2a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:10 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./pr_read_mem.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './pr_read_mem.sh' script. + +./pr_read_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./pr_read_mem.sh -noclean_files + +For more information on the script, please type './pr_read_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xcelium/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xcelium/file_info.txt new file mode 100644 index 0000000..fc38872 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xcelium/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +pr_read_mem.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xcelium/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xcelium/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xcelium/pr_read.coe b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xcelium/pr_read.coe new file mode 100755 index 0000000..b9ccb93 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xcelium/pr_read.coe @@ -0,0 +1,15 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010000000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001011000001100101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001001000001000101, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xcelium/pr_read_mem.mif b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xcelium/pr_read_mem.mif new file mode 100755 index 0000000..ef3787e --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xcelium/pr_read_mem.mif @@ -0,0 +1,13 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010000000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001011000001100101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001001000001000101 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xcelium/pr_read_mem.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xcelium/pr_read_mem.sh new file mode 100755 index 0000000..7d32b35 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xcelium/pr_read_mem.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : pr_read_mem.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:10 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: pr_read_mem.sh [-help] +# usage: pr_read_mem.sh [-lib_map_path] +# usage: pr_read_mem.sh [-noclean_files] +# usage: pr_read_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'pr_read_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "pr_read_mem.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.pr_read_mem \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./pr_read_mem.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./pr_read_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: pr_read_mem.sh [-help]\n\ +Usage: pr_read_mem.sh [-lib_map_path]\n\ +Usage: pr_read_mem.sh [-reset_run]\n\ +Usage: pr_read_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xcelium/run.f b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xcelium/run.f new file mode 100644 index 0000000..e730a7f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xcelium/run.f @@ -0,0 +1,18 @@ +-makelib xcelium_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xcelium/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xcelium/summary.log new file mode 100755 index 0000000..abd7c4a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xcelium/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [16] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xsim/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xsim/README.txt new file mode 100644 index 0000000..1c80f61 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:10 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./pr_read_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './pr_read_mem.sh' script. + +./pr_read_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./pr_read_mem.sh -noclean_files + +For more information on the script, please type './pr_read_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xsim/XUPVVH.smi b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xsim/XUPVVH.smi new file mode 100644 index 0000000..7951bb9 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xsim/XUPVVH.smi @@ -0,0 +1,30 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2019.2 (64-bit) --> +<!-- SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 --> +<!-- --> +<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --> +<!-- Nov 6 2019 --> +<!-- --> +<!-- This file is generated by the software with the Tcl write_mem_info command. --> +<!-- Do not edit this file. --> + +<MemInfoSimulation Version="1" Minor="1"> + <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I"> + <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_ADDR_SPACE" ECC="NONE" Begin="0" End="98303"> + <BusBlock> + <BitLane MemType="lmb_bram_I_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303"> + <DataWidth MSB="31" LSB="0"/> + <AddressRange Begin="0" End="16383"/> + <Parity ON="false" NumBits="0"/> + <MemFile Name="bd_9f2c_lmb_bram_I_0.mem"/> + </BitLane> + </BusBlock> + </AddressSpace> + </Processor> + <Config> + <Option Name="Part" Val="xcvu37p-fsvh2892-2-e"/> + </Config> + <DRC> + <Rule Name="RDADDRCHANGE" Val="false"/> + </DRC> +</MemInfoSimulation> diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xsim/cmd.tcl b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xsim/cmd.tcl new file mode 100644 index 0000000..eef7a0f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xsim/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xsim/file_info.txt new file mode 100644 index 0000000..ddeb1a7 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xsim/file_info.txt @@ -0,0 +1,2 @@ +pr_read_mem.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xsim/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xsim/pr_read.coe b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xsim/pr_read.coe new file mode 100755 index 0000000..b9ccb93 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xsim/pr_read.coe @@ -0,0 +1,15 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010000000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001011000001100101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001001000001000101, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xsim/pr_read_mem.mif b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xsim/pr_read_mem.mif new file mode 100755 index 0000000..ef3787e --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xsim/pr_read_mem.mif @@ -0,0 +1,13 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010000000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001011000001100101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001001000001000101 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xsim/pr_read_mem.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xsim/pr_read_mem.sh new file mode 100755 index 0000000..3c4fbfc --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xsim/pr_read_mem.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : pr_read_mem.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:10 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: pr_read_mem.sh [-help] +# usage: pr_read_mem.sh [-lib_map_path] +# usage: pr_read_mem.sh [-noclean_files] +# usage: pr_read_mem.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.2/tps/boost_1_64_0 +xvlog_opts="--relax" + + +# Script info +echo -e "pr_read_mem.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + xelab --relax --debug typical --mt auto -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot pr_read_mem xil_defaultlib.pr_read_mem xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + xsim pr_read_mem -key {Behavioral:sim_1:Functional:pr_read_mem} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./pr_read_mem.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.2/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb pr_read_mem.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./pr_read_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: pr_read_mem.sh [-help]\n\ +Usage: pr_read_mem.sh [-lib_map_path]\n\ +Usage: pr_read_mem.sh [-reset_run]\n\ +Usage: pr_read_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xsim/protoinst_files/bd_9f2c.protoinst b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xsim/protoinst_files/bd_9f2c.protoinst new file mode 100644 index 0000000..cf73fce --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xsim/protoinst_files/bd_9f2c.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_9f2c": { + "proto_instances": { + } + } + } +} diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xsim/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xsim/summary.log new file mode 100755 index 0000000..abd7c4a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xsim/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [16] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xsim/vlog.prj b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xsim/vlog.prj new file mode 100644 index 0000000..924f620 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_read_mem/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib \ +"../../../../XUPVVH.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/README.txt new file mode 100644 index 0000000..3cd3d87 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +<current_working_directory>/export_sim/<simulator> + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +<simulation_top>.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +<ip-name>.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/activehdl/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/activehdl/README.txt new file mode 100644 index 0000000..1546e48 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:17 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./pr_ref_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './pr_ref_mem.sh' script. + +./pr_ref_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./pr_ref_mem.sh -noclean_files + +For more information on the script, please type './pr_ref_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/activehdl/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/activehdl/compile.do new file mode 100644 index 0000000..d46ef4e --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/activehdl/compile.do @@ -0,0 +1,28 @@ +vlib work +vlib activehdl + +vlib activehdl/xpm +vlib activehdl/blk_mem_gen_v8_4_4 +vlib activehdl/xil_defaultlib + +vmap xpm activehdl/xpm +vmap blk_mem_gen_v8_4_4 activehdl/blk_mem_gen_v8_4_4 +vmap xil_defaultlib activehdl/xil_defaultlib + +vlog -work xpm -sv2k12 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 \ +"../../../../XUPVVH.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/activehdl/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/activehdl/file_info.txt new file mode 100644 index 0000000..4b47731 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/activehdl/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +pr_ref_mem.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/activehdl/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/activehdl/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/activehdl/pr_ref.coe b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/activehdl/pr_ref.coe new file mode 100755 index 0000000..8b0a9e1 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/activehdl/pr_ref.coe @@ -0,0 +1,51 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001101000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/activehdl/pr_ref_mem.mif b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/activehdl/pr_ref_mem.mif new file mode 100755 index 0000000..b3e8583 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/activehdl/pr_ref_mem.mif @@ -0,0 +1,49 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010100000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001101000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/activehdl/pr_ref_mem.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/activehdl/pr_ref_mem.sh new file mode 100755 index 0000000..025c513 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/activehdl/pr_ref_mem.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : pr_ref_mem.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:17 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: pr_ref_mem.sh [-help] +# usage: pr_ref_mem.sh [-lib_map_path] +# usage: pr_ref_mem.sh [-noclean_files] +# usage: pr_ref_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'pr_ref_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "pr_ref_mem.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./pr_ref_mem.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./pr_ref_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: pr_ref_mem.sh [-help]\n\ +Usage: pr_ref_mem.sh [-lib_map_path]\n\ +Usage: pr_ref_mem.sh [-reset_run]\n\ +Usage: pr_ref_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/activehdl/pr_ref_mem.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/activehdl/pr_ref_mem.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/activehdl/pr_ref_mem.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/activehdl/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/activehdl/simulate.do new file mode 100644 index 0000000..d9ec929 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+pr_ref_mem -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.pr_ref_mem xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {pr_ref_mem.udo} + +run -all + +endsim + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/activehdl/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/activehdl/summary.log new file mode 100755 index 0000000..7930542 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/activehdl/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [64] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/activehdl/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/activehdl/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/ies/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/ies/README.txt new file mode 100644 index 0000000..eaf55f8 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:17 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./pr_ref_mem.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './pr_ref_mem.sh' script. + +./pr_ref_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./pr_ref_mem.sh -noclean_files + +For more information on the script, please type './pr_ref_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/ies/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/ies/file_info.txt new file mode 100644 index 0000000..4b47731 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/ies/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +pr_ref_mem.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/ies/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/ies/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/ies/pr_ref.coe b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/ies/pr_ref.coe new file mode 100755 index 0000000..8b0a9e1 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/ies/pr_ref.coe @@ -0,0 +1,51 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001101000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/ies/pr_ref_mem.mif b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/ies/pr_ref_mem.mif new file mode 100755 index 0000000..b3e8583 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/ies/pr_ref_mem.mif @@ -0,0 +1,49 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010100000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001101000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/ies/pr_ref_mem.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/ies/pr_ref_mem.sh new file mode 100755 index 0000000..ca61e4a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/ies/pr_ref_mem.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : pr_ref_mem.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:17 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: pr_ref_mem.sh [-help] +# usage: pr_ref_mem.sh [-lib_map_path] +# usage: pr_ref_mem.sh [-noclean_files] +# usage: pr_ref_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'pr_ref_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "pr_ref_mem.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.pr_ref_mem \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./pr_ref_mem.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./pr_ref_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: pr_ref_mem.sh [-help]\n\ +Usage: pr_ref_mem.sh [-lib_map_path]\n\ +Usage: pr_ref_mem.sh [-reset_run]\n\ +Usage: pr_ref_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/ies/run.f b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/ies/run.f new file mode 100644 index 0000000..6b0f28e --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/ies/run.f @@ -0,0 +1,18 @@ +-makelib ies_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/ies/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/ies/summary.log new file mode 100755 index 0000000..7930542 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/ies/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [64] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/modelsim/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/modelsim/README.txt new file mode 100644 index 0000000..1546e48 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:17 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./pr_ref_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './pr_ref_mem.sh' script. + +./pr_ref_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./pr_ref_mem.sh -noclean_files + +For more information on the script, please type './pr_ref_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/modelsim/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/modelsim/compile.do new file mode 100644 index 0000000..366ec80 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/modelsim/compile.do @@ -0,0 +1,28 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xpm +vlib modelsim_lib/msim/blk_mem_gen_v8_4_4 +vlib modelsim_lib/msim/xil_defaultlib + +vmap xpm modelsim_lib/msim/xpm +vmap blk_mem_gen_v8_4_4 modelsim_lib/msim/blk_mem_gen_v8_4_4 +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xpm -64 -incr -sv \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -64 -incr \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 -incr \ +"../../../../XUPVVH.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/modelsim/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/modelsim/file_info.txt new file mode 100644 index 0000000..4b47731 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/modelsim/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +pr_ref_mem.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/modelsim/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/modelsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref.coe b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref.coe new file mode 100755 index 0000000..8b0a9e1 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref.coe @@ -0,0 +1,51 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001101000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref_mem.mif b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref_mem.mif new file mode 100755 index 0000000..b3e8583 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref_mem.mif @@ -0,0 +1,49 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010100000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001101000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref_mem.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref_mem.sh new file mode 100755 index 0000000..99acece --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref_mem.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : pr_ref_mem.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:17 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: pr_ref_mem.sh [-help] +# usage: pr_ref_mem.sh [-lib_map_path] +# usage: pr_ref_mem.sh [-noclean_files] +# usage: pr_ref_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'pr_ref_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "pr_ref_mem.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./pr_ref_mem.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/modelsim" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./pr_ref_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: pr_ref_mem.sh [-help]\n\ +Usage: pr_ref_mem.sh [-lib_map_path]\n\ +Usage: pr_ref_mem.sh [-reset_run]\n\ +Usage: pr_ref_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref_mem.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref_mem.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref_mem.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/modelsim/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/modelsim/simulate.do new file mode 100644 index 0000000..0c19fbb --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.pr_ref_mem xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {pr_ref_mem.udo} + +run -all + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/modelsim/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/modelsim/summary.log new file mode 100755 index 0000000..7930542 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/modelsim/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [64] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/modelsim/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/modelsim/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/README.txt new file mode 100644 index 0000000..1546e48 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:17 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./pr_ref_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './pr_ref_mem.sh' script. + +./pr_ref_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./pr_ref_mem.sh -noclean_files + +For more information on the script, please type './pr_ref_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/compile.do new file mode 100644 index 0000000..6bbf0cc --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/compile.do @@ -0,0 +1,28 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xpm +vlib questa_lib/msim/blk_mem_gen_v8_4_4 +vlib questa_lib/msim/xil_defaultlib + +vmap xpm questa_lib/msim/xpm +vmap blk_mem_gen_v8_4_4 questa_lib/msim/blk_mem_gen_v8_4_4 +vmap xil_defaultlib questa_lib/msim/xil_defaultlib + +vlog -work xpm -64 -sv \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -64 \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 \ +"../../../../XUPVVH.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/elaborate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/elaborate.do new file mode 100644 index 0000000..324b75a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.pr_ref_mem xil_defaultlib.glbl -o pr_ref_mem_opt diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/file_info.txt new file mode 100644 index 0000000..4b47731 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +pr_ref_mem.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref.coe b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref.coe new file mode 100755 index 0000000..8b0a9e1 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref.coe @@ -0,0 +1,51 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001101000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref_mem.mif b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref_mem.mif new file mode 100755 index 0000000..b3e8583 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref_mem.mif @@ -0,0 +1,49 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010100000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001101000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref_mem.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref_mem.sh new file mode 100755 index 0000000..1a52c8b --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref_mem.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : pr_ref_mem.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:17 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: pr_ref_mem.sh [-help] +# usage: pr_ref_mem.sh [-lib_map_path] +# usage: pr_ref_mem.sh [-noclean_files] +# usage: pr_ref_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'pr_ref_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "pr_ref_mem.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./pr_ref_mem.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./pr_ref_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: pr_ref_mem.sh [-help]\n\ +Usage: pr_ref_mem.sh [-lib_map_path]\n\ +Usage: pr_ref_mem.sh [-reset_run]\n\ +Usage: pr_ref_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref_mem.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref_mem.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref_mem.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/simulate.do new file mode 100644 index 0000000..ce29775 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib pr_ref_mem_opt + +do {wave.do} + +view wave +view structure +view signals + +do {pr_ref_mem.udo} + +run -all + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/summary.log new file mode 100755 index 0000000..7930542 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [64] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/riviera/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/riviera/README.txt new file mode 100644 index 0000000..1546e48 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:17 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./pr_ref_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './pr_ref_mem.sh' script. + +./pr_ref_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./pr_ref_mem.sh -noclean_files + +For more information on the script, please type './pr_ref_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/riviera/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/riviera/compile.do new file mode 100644 index 0000000..6c4eaa1 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/riviera/compile.do @@ -0,0 +1,28 @@ +vlib work +vlib riviera + +vlib riviera/xpm +vlib riviera/blk_mem_gen_v8_4_4 +vlib riviera/xil_defaultlib + +vmap xpm riviera/xpm +vmap blk_mem_gen_v8_4_4 riviera/blk_mem_gen_v8_4_4 +vmap xil_defaultlib riviera/xil_defaultlib + +vlog -work xpm -sv2k12 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 \ +"../../../../XUPVVH.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/riviera/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/riviera/file_info.txt new file mode 100644 index 0000000..4b47731 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/riviera/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +pr_ref_mem.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/riviera/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/riviera/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/riviera/pr_ref.coe b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/riviera/pr_ref.coe new file mode 100755 index 0000000..8b0a9e1 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/riviera/pr_ref.coe @@ -0,0 +1,51 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001101000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/riviera/pr_ref_mem.mif b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/riviera/pr_ref_mem.mif new file mode 100755 index 0000000..b3e8583 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/riviera/pr_ref_mem.mif @@ -0,0 +1,49 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010100000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001101000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/riviera/pr_ref_mem.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/riviera/pr_ref_mem.sh new file mode 100755 index 0000000..3611033 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/riviera/pr_ref_mem.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : pr_ref_mem.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:17 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: pr_ref_mem.sh [-help] +# usage: pr_ref_mem.sh [-lib_map_path] +# usage: pr_ref_mem.sh [-noclean_files] +# usage: pr_ref_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'pr_ref_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "pr_ref_mem.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./pr_ref_mem.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./pr_ref_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: pr_ref_mem.sh [-help]\n\ +Usage: pr_ref_mem.sh [-lib_map_path]\n\ +Usage: pr_ref_mem.sh [-reset_run]\n\ +Usage: pr_ref_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/riviera/pr_ref_mem.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/riviera/pr_ref_mem.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/riviera/pr_ref_mem.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/riviera/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/riviera/simulate.do new file mode 100644 index 0000000..d9ec929 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+pr_ref_mem -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.pr_ref_mem xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {pr_ref_mem.udo} + +run -all + +endsim + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/riviera/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/riviera/summary.log new file mode 100755 index 0000000..7930542 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/riviera/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [64] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/riviera/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/riviera/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/vcs/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/vcs/README.txt new file mode 100644 index 0000000..1546e48 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:17 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./pr_ref_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './pr_ref_mem.sh' script. + +./pr_ref_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./pr_ref_mem.sh -noclean_files + +For more information on the script, please type './pr_ref_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/vcs/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/vcs/file_info.txt new file mode 100644 index 0000000..4b47731 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/vcs/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +pr_ref_mem.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/vcs/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/vcs/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/vcs/pr_ref.coe b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/vcs/pr_ref.coe new file mode 100755 index 0000000..8b0a9e1 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/vcs/pr_ref.coe @@ -0,0 +1,51 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001101000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/vcs/pr_ref_mem.mif b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/vcs/pr_ref_mem.mif new file mode 100755 index 0000000..b3e8583 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/vcs/pr_ref_mem.mif @@ -0,0 +1,49 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010100000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001101000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/vcs/pr_ref_mem.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/vcs/pr_ref_mem.sh new file mode 100755 index 0000000..5b376ae --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/vcs/pr_ref_mem.sh @@ -0,0 +1,235 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : pr_ref_mem.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:17 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: pr_ref_mem.sh [-help] +# usage: pr_ref_mem.sh [-lib_map_path] +# usage: pr_ref_mem.sh [-noclean_files] +# usage: pr_ref_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'pr_ref_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "pr_ref_mem.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + vlogan -work xpm $vlogan_opts -sverilog \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work blk_mem_gen_v8_4_4 $vlogan_opts +v2k \ + "$ref_dir/../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.pr_ref_mem xil_defaultlib.glbl -o pr_ref_mem_simv +} + +# RUN_STEP: <simulate> +simulate() +{ + ./pr_ref_mem_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./pr_ref_mem.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/vcs" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key pr_ref_mem_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc pr_ref_mem_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./pr_ref_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: pr_ref_mem.sh [-help]\n\ +Usage: pr_ref_mem.sh [-lib_map_path]\n\ +Usage: pr_ref_mem.sh [-reset_run]\n\ +Usage: pr_ref_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/vcs/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/vcs/simulate.do new file mode 100644 index 0000000..58afc78 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/vcs/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/vcs/summary.log new file mode 100755 index 0000000..7930542 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/vcs/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [64] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xcelium/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xcelium/README.txt new file mode 100644 index 0000000..eaf55f8 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:17 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./pr_ref_mem.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './pr_ref_mem.sh' script. + +./pr_ref_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./pr_ref_mem.sh -noclean_files + +For more information on the script, please type './pr_ref_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xcelium/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xcelium/file_info.txt new file mode 100644 index 0000000..4b47731 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xcelium/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +pr_ref_mem.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xcelium/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xcelium/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xcelium/pr_ref.coe b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xcelium/pr_ref.coe new file mode 100755 index 0000000..8b0a9e1 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xcelium/pr_ref.coe @@ -0,0 +1,51 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001101000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xcelium/pr_ref_mem.mif b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xcelium/pr_ref_mem.mif new file mode 100755 index 0000000..b3e8583 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xcelium/pr_ref_mem.mif @@ -0,0 +1,49 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010100000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001101000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xcelium/pr_ref_mem.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xcelium/pr_ref_mem.sh new file mode 100755 index 0000000..df1b870 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xcelium/pr_ref_mem.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : pr_ref_mem.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:17 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: pr_ref_mem.sh [-help] +# usage: pr_ref_mem.sh [-lib_map_path] +# usage: pr_ref_mem.sh [-noclean_files] +# usage: pr_ref_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'pr_ref_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "pr_ref_mem.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.pr_ref_mem \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./pr_ref_mem.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./pr_ref_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: pr_ref_mem.sh [-help]\n\ +Usage: pr_ref_mem.sh [-lib_map_path]\n\ +Usage: pr_ref_mem.sh [-reset_run]\n\ +Usage: pr_ref_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xcelium/run.f b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xcelium/run.f new file mode 100644 index 0000000..0bc822c --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xcelium/run.f @@ -0,0 +1,18 @@ +-makelib xcelium_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xcelium/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xcelium/summary.log new file mode 100755 index 0000000..7930542 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xcelium/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [64] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xsim/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xsim/README.txt new file mode 100644 index 0000000..1546e48 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:17 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./pr_ref_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './pr_ref_mem.sh' script. + +./pr_ref_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./pr_ref_mem.sh -noclean_files + +For more information on the script, please type './pr_ref_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xsim/XUPVVH.smi b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xsim/XUPVVH.smi new file mode 100644 index 0000000..7951bb9 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xsim/XUPVVH.smi @@ -0,0 +1,30 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2019.2 (64-bit) --> +<!-- SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 --> +<!-- --> +<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --> +<!-- Nov 6 2019 --> +<!-- --> +<!-- This file is generated by the software with the Tcl write_mem_info command. --> +<!-- Do not edit this file. --> + +<MemInfoSimulation Version="1" Minor="1"> + <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I"> + <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_ADDR_SPACE" ECC="NONE" Begin="0" End="98303"> + <BusBlock> + <BitLane MemType="lmb_bram_I_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303"> + <DataWidth MSB="31" LSB="0"/> + <AddressRange Begin="0" End="16383"/> + <Parity ON="false" NumBits="0"/> + <MemFile Name="bd_9f2c_lmb_bram_I_0.mem"/> + </BitLane> + </BusBlock> + </AddressSpace> + </Processor> + <Config> + <Option Name="Part" Val="xcvu37p-fsvh2892-2-e"/> + </Config> + <DRC> + <Rule Name="RDADDRCHANGE" Val="false"/> + </DRC> +</MemInfoSimulation> diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xsim/cmd.tcl b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xsim/cmd.tcl new file mode 100644 index 0000000..eef7a0f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xsim/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xsim/file_info.txt new file mode 100644 index 0000000..d7b28f5 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xsim/file_info.txt @@ -0,0 +1,2 @@ +pr_ref_mem.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xsim/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xsim/pr_ref.coe b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xsim/pr_ref.coe new file mode 100755 index 0000000..8b0a9e1 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xsim/pr_ref.coe @@ -0,0 +1,51 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001101000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xsim/pr_ref_mem.mif b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xsim/pr_ref_mem.mif new file mode 100755 index 0000000..b3e8583 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xsim/pr_ref_mem.mif @@ -0,0 +1,49 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010100000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001101000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xsim/pr_ref_mem.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xsim/pr_ref_mem.sh new file mode 100755 index 0000000..c551c86 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xsim/pr_ref_mem.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : pr_ref_mem.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:17 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: pr_ref_mem.sh [-help] +# usage: pr_ref_mem.sh [-lib_map_path] +# usage: pr_ref_mem.sh [-noclean_files] +# usage: pr_ref_mem.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.2/tps/boost_1_64_0 +xvlog_opts="--relax" + + +# Script info +echo -e "pr_ref_mem.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + xelab --relax --debug typical --mt auto -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot pr_ref_mem xil_defaultlib.pr_ref_mem xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + xsim pr_ref_mem -key {Behavioral:sim_1:Functional:pr_ref_mem} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./pr_ref_mem.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.2/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb pr_ref_mem.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./pr_ref_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: pr_ref_mem.sh [-help]\n\ +Usage: pr_ref_mem.sh [-lib_map_path]\n\ +Usage: pr_ref_mem.sh [-reset_run]\n\ +Usage: pr_ref_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xsim/protoinst_files/bd_9f2c.protoinst b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xsim/protoinst_files/bd_9f2c.protoinst new file mode 100644 index 0000000..cf73fce --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xsim/protoinst_files/bd_9f2c.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_9f2c": { + "proto_instances": { + } + } + } +} diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xsim/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xsim/summary.log new file mode 100755 index 0000000..7930542 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xsim/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [64] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xsim/vlog.prj b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xsim/vlog.prj new file mode 100644 index 0000000..055265a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/pr_ref_mem/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib \ +"../../../../XUPVVH.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/README.txt new file mode 100644 index 0000000..3cd3d87 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +<current_working_directory>/export_sim/<simulator> + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +<simulation_top>.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +<ip-name>.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/activehdl/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/activehdl/README.txt new file mode 100644 index 0000000..5df63e8 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:28 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rdback_fifo.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rdback_fifo.sh' script. + +./rdback_fifo.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rdback_fifo.sh -noclean_files + +For more information on the script, please type './rdback_fifo.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/activehdl/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/activehdl/compile.do new file mode 100644 index 0000000..0058794 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/activehdl/compile.do @@ -0,0 +1,34 @@ +vlib work +vlib activehdl + +vlib activehdl/xpm +vlib activehdl/fifo_generator_v13_2_5 +vlib activehdl/xil_defaultlib + +vmap xpm activehdl/xpm +vmap fifo_generator_v13_2_5 activehdl/fifo_generator_v13_2_5 +vmap xil_defaultlib activehdl/xil_defaultlib + +vlog -work xpm -sv2k12 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work fifo_generator_v13_2_5 -v2k5 \ +"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \ + +vcom -work fifo_generator_v13_2_5 -93 \ +"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \ + +vlog -work fifo_generator_v13_2_5 -v2k5 \ +"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \ + +vlog -work xil_defaultlib -v2k5 \ +"../../../../XUPVVH.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/activehdl/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/activehdl/file_info.txt new file mode 100644 index 0000000..211c17c --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/activehdl/file_info.txt @@ -0,0 +1,9 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/simulation/fifo_generator_vlog_beh.v, +fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd, +fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v, +rdback_fifo.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/activehdl/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/activehdl/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/activehdl/rdback_fifo.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/activehdl/rdback_fifo.sh new file mode 100755 index 0000000..b1be1b6 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/activehdl/rdback_fifo.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : rdback_fifo.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:28 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: rdback_fifo.sh [-help] +# usage: rdback_fifo.sh [-lib_map_path] +# usage: rdback_fifo.sh [-noclean_files] +# usage: rdback_fifo.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'rdback_fifo.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "rdback_fifo.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rdback_fifo.sh [-help]\n\ +Usage: rdback_fifo.sh [-lib_map_path]\n\ +Usage: rdback_fifo.sh [-reset_run]\n\ +Usage: rdback_fifo.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/activehdl/rdback_fifo.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/activehdl/rdback_fifo.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/activehdl/rdback_fifo.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/activehdl/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/activehdl/simulate.do new file mode 100644 index 0000000..e6172ba --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+rdback_fifo -L xpm -L fifo_generator_v13_2_5 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.rdback_fifo xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {rdback_fifo.udo} + +run -all + +endsim + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/activehdl/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/activehdl/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/ies/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/ies/README.txt new file mode 100644 index 0000000..d5d248d --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:28 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rdback_fifo.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rdback_fifo.sh' script. + +./rdback_fifo.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rdback_fifo.sh -noclean_files + +For more information on the script, please type './rdback_fifo.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/ies/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/ies/file_info.txt new file mode 100644 index 0000000..211c17c --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/ies/file_info.txt @@ -0,0 +1,9 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/simulation/fifo_generator_vlog_beh.v, +fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd, +fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v, +rdback_fifo.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/ies/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/ies/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/ies/rdback_fifo.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/ies/rdback_fifo.sh new file mode 100755 index 0000000..66ebd20 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/ies/rdback_fifo.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : rdback_fifo.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:28 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: rdback_fifo.sh [-help] +# usage: rdback_fifo.sh [-lib_map_path] +# usage: rdback_fifo.sh [-noclean_files] +# usage: rdback_fifo.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'rdback_fifo.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xpm fifo_generator_v13_2_5 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "rdback_fifo.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.rdback_fifo \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rdback_fifo.sh [-help]\n\ +Usage: rdback_fifo.sh [-lib_map_path]\n\ +Usage: rdback_fifo.sh [-reset_run]\n\ +Usage: rdback_fifo.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/ies/run.f b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/ies/run.f new file mode 100644 index 0000000..5fcdc3d --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/ies/run.f @@ -0,0 +1,24 @@ +-makelib ies_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/fifo_generator_v13_2_5 \ + "../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \ +-endlib +-makelib ies_lib/fifo_generator_v13_2_5 \ + "../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \ +-endlib +-makelib ies_lib/fifo_generator_v13_2_5 \ + "../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/modelsim/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/modelsim/README.txt new file mode 100644 index 0000000..5df63e8 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:28 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rdback_fifo.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rdback_fifo.sh' script. + +./rdback_fifo.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rdback_fifo.sh -noclean_files + +For more information on the script, please type './rdback_fifo.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/modelsim/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/modelsim/compile.do new file mode 100644 index 0000000..8bf6353 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/modelsim/compile.do @@ -0,0 +1,34 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xpm +vlib modelsim_lib/msim/fifo_generator_v13_2_5 +vlib modelsim_lib/msim/xil_defaultlib + +vmap xpm modelsim_lib/msim/xpm +vmap fifo_generator_v13_2_5 modelsim_lib/msim/fifo_generator_v13_2_5 +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xpm -64 -incr -sv \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work fifo_generator_v13_2_5 -64 -incr \ +"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \ + +vcom -work fifo_generator_v13_2_5 -64 -93 \ +"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \ + +vlog -work fifo_generator_v13_2_5 -64 -incr \ +"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \ + +vlog -work xil_defaultlib -64 -incr \ +"../../../../XUPVVH.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/modelsim/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/modelsim/file_info.txt new file mode 100644 index 0000000..211c17c --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/modelsim/file_info.txt @@ -0,0 +1,9 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/simulation/fifo_generator_vlog_beh.v, +fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd, +fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v, +rdback_fifo.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/modelsim/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/modelsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/modelsim/rdback_fifo.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/modelsim/rdback_fifo.sh new file mode 100755 index 0000000..f982428 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/modelsim/rdback_fifo.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : rdback_fifo.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:28 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: rdback_fifo.sh [-help] +# usage: rdback_fifo.sh [-lib_map_path] +# usage: rdback_fifo.sh [-noclean_files] +# usage: rdback_fifo.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'rdback_fifo.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "rdback_fifo.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/modelsim" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rdback_fifo.sh [-help]\n\ +Usage: rdback_fifo.sh [-lib_map_path]\n\ +Usage: rdback_fifo.sh [-reset_run]\n\ +Usage: rdback_fifo.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/modelsim/rdback_fifo.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/modelsim/rdback_fifo.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/modelsim/rdback_fifo.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/modelsim/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/modelsim/simulate.do new file mode 100644 index 0000000..520d481 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xpm -L fifo_generator_v13_2_5 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.rdback_fifo xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {rdback_fifo.udo} + +run -all + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/modelsim/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/modelsim/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/README.txt new file mode 100644 index 0000000..5df63e8 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:28 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rdback_fifo.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rdback_fifo.sh' script. + +./rdback_fifo.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rdback_fifo.sh -noclean_files + +For more information on the script, please type './rdback_fifo.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/compile.do new file mode 100644 index 0000000..c05b1c0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/compile.do @@ -0,0 +1,34 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xpm +vlib questa_lib/msim/fifo_generator_v13_2_5 +vlib questa_lib/msim/xil_defaultlib + +vmap xpm questa_lib/msim/xpm +vmap fifo_generator_v13_2_5 questa_lib/msim/fifo_generator_v13_2_5 +vmap xil_defaultlib questa_lib/msim/xil_defaultlib + +vlog -work xpm -64 -sv \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work fifo_generator_v13_2_5 -64 \ +"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \ + +vcom -work fifo_generator_v13_2_5 -64 -93 \ +"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \ + +vlog -work fifo_generator_v13_2_5 -64 \ +"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \ + +vlog -work xil_defaultlib -64 \ +"../../../../XUPVVH.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/elaborate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/elaborate.do new file mode 100644 index 0000000..f2543ff --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xpm -L fifo_generator_v13_2_5 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.rdback_fifo xil_defaultlib.glbl -o rdback_fifo_opt diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/file_info.txt new file mode 100644 index 0000000..211c17c --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/file_info.txt @@ -0,0 +1,9 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/simulation/fifo_generator_vlog_beh.v, +fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd, +fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v, +rdback_fifo.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/rdback_fifo.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/rdback_fifo.sh new file mode 100755 index 0000000..fce92ef --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/rdback_fifo.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : rdback_fifo.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:28 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: rdback_fifo.sh [-help] +# usage: rdback_fifo.sh [-lib_map_path] +# usage: rdback_fifo.sh [-noclean_files] +# usage: rdback_fifo.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'rdback_fifo.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "rdback_fifo.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rdback_fifo.sh [-help]\n\ +Usage: rdback_fifo.sh [-lib_map_path]\n\ +Usage: rdback_fifo.sh [-reset_run]\n\ +Usage: rdback_fifo.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/rdback_fifo.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/rdback_fifo.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/rdback_fifo.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/simulate.do new file mode 100644 index 0000000..1f469d6 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib rdback_fifo_opt + +do {wave.do} + +view wave +view structure +view signals + +do {rdback_fifo.udo} + +run -all + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/riviera/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/riviera/README.txt new file mode 100644 index 0000000..5df63e8 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:28 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rdback_fifo.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rdback_fifo.sh' script. + +./rdback_fifo.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rdback_fifo.sh -noclean_files + +For more information on the script, please type './rdback_fifo.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/riviera/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/riviera/compile.do new file mode 100644 index 0000000..1ac8aed --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/riviera/compile.do @@ -0,0 +1,34 @@ +vlib work +vlib riviera + +vlib riviera/xpm +vlib riviera/fifo_generator_v13_2_5 +vlib riviera/xil_defaultlib + +vmap xpm riviera/xpm +vmap fifo_generator_v13_2_5 riviera/fifo_generator_v13_2_5 +vmap xil_defaultlib riviera/xil_defaultlib + +vlog -work xpm -sv2k12 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work fifo_generator_v13_2_5 -v2k5 \ +"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \ + +vcom -work fifo_generator_v13_2_5 -93 \ +"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \ + +vlog -work fifo_generator_v13_2_5 -v2k5 \ +"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \ + +vlog -work xil_defaultlib -v2k5 \ +"../../../../XUPVVH.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/riviera/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/riviera/file_info.txt new file mode 100644 index 0000000..211c17c --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/riviera/file_info.txt @@ -0,0 +1,9 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/simulation/fifo_generator_vlog_beh.v, +fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd, +fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v, +rdback_fifo.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/riviera/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/riviera/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/riviera/rdback_fifo.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/riviera/rdback_fifo.sh new file mode 100755 index 0000000..2a5c5eb --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/riviera/rdback_fifo.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : rdback_fifo.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:28 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: rdback_fifo.sh [-help] +# usage: rdback_fifo.sh [-lib_map_path] +# usage: rdback_fifo.sh [-noclean_files] +# usage: rdback_fifo.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'rdback_fifo.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "rdback_fifo.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rdback_fifo.sh [-help]\n\ +Usage: rdback_fifo.sh [-lib_map_path]\n\ +Usage: rdback_fifo.sh [-reset_run]\n\ +Usage: rdback_fifo.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/riviera/rdback_fifo.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/riviera/rdback_fifo.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/riviera/rdback_fifo.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/riviera/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/riviera/simulate.do new file mode 100644 index 0000000..e6172ba --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+rdback_fifo -L xpm -L fifo_generator_v13_2_5 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.rdback_fifo xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {rdback_fifo.udo} + +run -all + +endsim + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/riviera/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/riviera/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/vcs/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/vcs/README.txt new file mode 100644 index 0000000..5df63e8 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:28 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rdback_fifo.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rdback_fifo.sh' script. + +./rdback_fifo.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rdback_fifo.sh -noclean_files + +For more information on the script, please type './rdback_fifo.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/vcs/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/vcs/file_info.txt new file mode 100644 index 0000000..211c17c --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/vcs/file_info.txt @@ -0,0 +1,9 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/simulation/fifo_generator_vlog_beh.v, +fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd, +fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v, +rdback_fifo.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/vcs/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/vcs/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/vcs/rdback_fifo.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/vcs/rdback_fifo.sh new file mode 100755 index 0000000..b77e3ce --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/vcs/rdback_fifo.sh @@ -0,0 +1,243 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : rdback_fifo.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:28 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: rdback_fifo.sh [-help] +# usage: rdback_fifo.sh [-lib_map_path] +# usage: rdback_fifo.sh [-noclean_files] +# usage: rdback_fifo.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'rdback_fifo.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xpm fifo_generator_v13_2_5 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "rdback_fifo.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + vlogan -work xpm $vlogan_opts -sverilog \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work fifo_generator_v13_2_5 $vlogan_opts +v2k \ + "$ref_dir/../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work fifo_generator_v13_2_5 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work fifo_generator_v13_2_5 $vlogan_opts +v2k \ + "$ref_dir/../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.rdback_fifo xil_defaultlib.glbl -o rdback_fifo_simv +} + +# RUN_STEP: <simulate> +simulate() +{ + ./rdback_fifo_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/vcs" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key rdback_fifo_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc rdback_fifo_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rdback_fifo.sh [-help]\n\ +Usage: rdback_fifo.sh [-lib_map_path]\n\ +Usage: rdback_fifo.sh [-reset_run]\n\ +Usage: rdback_fifo.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/vcs/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/vcs/simulate.do new file mode 100644 index 0000000..58afc78 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xcelium/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xcelium/README.txt new file mode 100644 index 0000000..d5d248d --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:28 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rdback_fifo.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rdback_fifo.sh' script. + +./rdback_fifo.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rdback_fifo.sh -noclean_files + +For more information on the script, please type './rdback_fifo.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xcelium/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xcelium/file_info.txt new file mode 100644 index 0000000..211c17c --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xcelium/file_info.txt @@ -0,0 +1,9 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/simulation/fifo_generator_vlog_beh.v, +fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd, +fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v, +rdback_fifo.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xcelium/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xcelium/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xcelium/rdback_fifo.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xcelium/rdback_fifo.sh new file mode 100755 index 0000000..dad4d60 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xcelium/rdback_fifo.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : rdback_fifo.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:28 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: rdback_fifo.sh [-help] +# usage: rdback_fifo.sh [-lib_map_path] +# usage: rdback_fifo.sh [-noclean_files] +# usage: rdback_fifo.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'rdback_fifo.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xpm fifo_generator_v13_2_5 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "rdback_fifo.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.rdback_fifo \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rdback_fifo.sh [-help]\n\ +Usage: rdback_fifo.sh [-lib_map_path]\n\ +Usage: rdback_fifo.sh [-reset_run]\n\ +Usage: rdback_fifo.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xcelium/run.f b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xcelium/run.f new file mode 100644 index 0000000..1b75a42 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xcelium/run.f @@ -0,0 +1,24 @@ +-makelib xcelium_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/fifo_generator_v13_2_5 \ + "../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \ +-endlib +-makelib xcelium_lib/fifo_generator_v13_2_5 \ + "../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \ +-endlib +-makelib xcelium_lib/fifo_generator_v13_2_5 \ + "../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xsim/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xsim/README.txt new file mode 100644 index 0000000..5df63e8 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:28 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rdback_fifo.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rdback_fifo.sh' script. + +./rdback_fifo.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rdback_fifo.sh -noclean_files + +For more information on the script, please type './rdback_fifo.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xsim/XUPVVH.smi b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xsim/XUPVVH.smi new file mode 100644 index 0000000..7951bb9 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xsim/XUPVVH.smi @@ -0,0 +1,30 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2019.2 (64-bit) --> +<!-- SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 --> +<!-- --> +<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --> +<!-- Nov 6 2019 --> +<!-- --> +<!-- This file is generated by the software with the Tcl write_mem_info command. --> +<!-- Do not edit this file. --> + +<MemInfoSimulation Version="1" Minor="1"> + <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I"> + <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_ADDR_SPACE" ECC="NONE" Begin="0" End="98303"> + <BusBlock> + <BitLane MemType="lmb_bram_I_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303"> + <DataWidth MSB="31" LSB="0"/> + <AddressRange Begin="0" End="16383"/> + <Parity ON="false" NumBits="0"/> + <MemFile Name="bd_9f2c_lmb_bram_I_0.mem"/> + </BitLane> + </BusBlock> + </AddressSpace> + </Processor> + <Config> + <Option Name="Part" Val="xcvu37p-fsvh2892-2-e"/> + </Config> + <DRC> + <Rule Name="RDADDRCHANGE" Val="false"/> + </DRC> +</MemInfoSimulation> diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xsim/cmd.tcl b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xsim/cmd.tcl new file mode 100644 index 0000000..eef7a0f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xsim/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xsim/file_info.txt new file mode 100644 index 0000000..0b4b095 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xsim/file_info.txt @@ -0,0 +1,2 @@ +rdback_fifo.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xsim/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xsim/protoinst_files/bd_9f2c.protoinst b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xsim/protoinst_files/bd_9f2c.protoinst new file mode 100644 index 0000000..cf73fce --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xsim/protoinst_files/bd_9f2c.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_9f2c": { + "proto_instances": { + } + } + } +} diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xsim/rdback_fifo.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xsim/rdback_fifo.sh new file mode 100755 index 0000000..367b0c9 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xsim/rdback_fifo.sh @@ -0,0 +1,214 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : rdback_fifo.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:28 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: rdback_fifo.sh [-help] +# usage: rdback_fifo.sh [-lib_map_path] +# usage: rdback_fifo.sh [-noclean_files] +# usage: rdback_fifo.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.2/tps/boost_1_64_0 +xvlog_opts="--relax" +xvhdl_opts="--relax" + + +# Script info +echo -e "rdback_fifo.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + xvhdl $xvhdl_opts -prj vhdl.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + xelab --relax --debug typical --mt auto -L fifo_generator_v13_2_5 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot rdback_fifo xil_defaultlib.rdback_fifo xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + xsim rdback_fifo -key {Behavioral:sim_1:Functional:rdback_fifo} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.2/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb rdback_fifo.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rdback_fifo.sh [-help]\n\ +Usage: rdback_fifo.sh [-lib_map_path]\n\ +Usage: rdback_fifo.sh [-reset_run]\n\ +Usage: rdback_fifo.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xsim/vhdl.prj b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xsim/vhdl.prj new file mode 100644 index 0000000..359cbd5 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xsim/vhdl.prj @@ -0,0 +1,2 @@ + +nosort diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xsim/vlog.prj b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xsim/vlog.prj new file mode 100644 index 0000000..6b0f840 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib \ +"../../../../XUPVVH.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/README.txt new file mode 100644 index 0000000..3cd3d87 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +<current_working_directory>/export_sim/<simulator> + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +<simulation_top>.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +<ip-name>.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/activehdl/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/activehdl/README.txt new file mode 100644 index 0000000..fe38b80 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:38 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./scratchpad.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './scratchpad.sh' script. + +./scratchpad.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./scratchpad.sh -noclean_files + +For more information on the script, please type './scratchpad.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/activehdl/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/activehdl/compile.do new file mode 100644 index 0000000..41565dd --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/activehdl/compile.do @@ -0,0 +1,28 @@ +vlib work +vlib activehdl + +vlib activehdl/xpm +vlib activehdl/blk_mem_gen_v8_4_4 +vlib activehdl/xil_defaultlib + +vmap xpm activehdl/xpm +vmap blk_mem_gen_v8_4_4 activehdl/blk_mem_gen_v8_4_4 +vmap xil_defaultlib activehdl/xil_defaultlib + +vlog -work xpm -sv2k12 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 \ +"../../../../XUPVVH.srcs/sources_1/ip/scratchpad/sim/scratchpad.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/activehdl/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/activehdl/file_info.txt new file mode 100644 index 0000000..8d9f28f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/activehdl/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +scratchpad.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/scratchpad/sim/scratchpad.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/activehdl/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/activehdl/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/activehdl/scratchpad.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/activehdl/scratchpad.sh new file mode 100755 index 0000000..7073cb4 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/activehdl/scratchpad.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : scratchpad.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:38 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: scratchpad.sh [-help] +# usage: scratchpad.sh [-lib_map_path] +# usage: scratchpad.sh [-noclean_files] +# usage: scratchpad.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'scratchpad.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "scratchpad.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./scratchpad.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./scratchpad.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: scratchpad.sh [-help]\n\ +Usage: scratchpad.sh [-lib_map_path]\n\ +Usage: scratchpad.sh [-reset_run]\n\ +Usage: scratchpad.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/activehdl/scratchpad.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/activehdl/scratchpad.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/activehdl/scratchpad.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/activehdl/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/activehdl/simulate.do new file mode 100644 index 0000000..c3c5ac1 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+scratchpad -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.scratchpad xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {scratchpad.udo} + +run -all + +endsim + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/activehdl/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/activehdl/summary.log new file mode 100755 index 0000000..28dc68a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/activehdl/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [32] +Port A Write Width : [32] +Memory Depth : [1024] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 2.119075 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/activehdl/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/activehdl/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/ies/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/ies/README.txt new file mode 100644 index 0000000..d2dc2e7 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:38 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./scratchpad.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './scratchpad.sh' script. + +./scratchpad.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./scratchpad.sh -noclean_files + +For more information on the script, please type './scratchpad.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/ies/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/ies/file_info.txt new file mode 100644 index 0000000..8d9f28f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/ies/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +scratchpad.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/scratchpad/sim/scratchpad.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/ies/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/ies/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/ies/run.f b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/ies/run.f new file mode 100644 index 0000000..81ab485 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/ies/run.f @@ -0,0 +1,18 @@ +-makelib ies_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/scratchpad/sim/scratchpad.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/ies/scratchpad.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/ies/scratchpad.sh new file mode 100755 index 0000000..4da4c5d --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/ies/scratchpad.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : scratchpad.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:38 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: scratchpad.sh [-help] +# usage: scratchpad.sh [-lib_map_path] +# usage: scratchpad.sh [-noclean_files] +# usage: scratchpad.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'scratchpad.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "scratchpad.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.scratchpad \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./scratchpad.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./scratchpad.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: scratchpad.sh [-help]\n\ +Usage: scratchpad.sh [-lib_map_path]\n\ +Usage: scratchpad.sh [-reset_run]\n\ +Usage: scratchpad.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/ies/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/ies/summary.log new file mode 100755 index 0000000..28dc68a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/ies/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [32] +Port A Write Width : [32] +Memory Depth : [1024] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 2.119075 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/modelsim/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/modelsim/README.txt new file mode 100644 index 0000000..fe38b80 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:38 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./scratchpad.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './scratchpad.sh' script. + +./scratchpad.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./scratchpad.sh -noclean_files + +For more information on the script, please type './scratchpad.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/modelsim/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/modelsim/compile.do new file mode 100644 index 0000000..92227c8 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/modelsim/compile.do @@ -0,0 +1,28 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xpm +vlib modelsim_lib/msim/blk_mem_gen_v8_4_4 +vlib modelsim_lib/msim/xil_defaultlib + +vmap xpm modelsim_lib/msim/xpm +vmap blk_mem_gen_v8_4_4 modelsim_lib/msim/blk_mem_gen_v8_4_4 +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xpm -64 -incr -sv \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -64 -incr \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 -incr \ +"../../../../XUPVVH.srcs/sources_1/ip/scratchpad/sim/scratchpad.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/modelsim/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/modelsim/file_info.txt new file mode 100644 index 0000000..8d9f28f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/modelsim/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +scratchpad.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/scratchpad/sim/scratchpad.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/modelsim/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/modelsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/modelsim/scratchpad.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/modelsim/scratchpad.sh new file mode 100755 index 0000000..d352884 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/modelsim/scratchpad.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : scratchpad.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:38 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: scratchpad.sh [-help] +# usage: scratchpad.sh [-lib_map_path] +# usage: scratchpad.sh [-noclean_files] +# usage: scratchpad.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'scratchpad.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "scratchpad.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./scratchpad.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/modelsim" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./scratchpad.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: scratchpad.sh [-help]\n\ +Usage: scratchpad.sh [-lib_map_path]\n\ +Usage: scratchpad.sh [-reset_run]\n\ +Usage: scratchpad.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/modelsim/scratchpad.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/modelsim/scratchpad.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/modelsim/scratchpad.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/modelsim/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/modelsim/simulate.do new file mode 100644 index 0000000..c150939 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.scratchpad xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {scratchpad.udo} + +run -all + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/modelsim/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/modelsim/summary.log new file mode 100755 index 0000000..28dc68a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/modelsim/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [32] +Port A Write Width : [32] +Memory Depth : [1024] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 2.119075 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/modelsim/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/modelsim/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/questa/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/questa/README.txt new file mode 100644 index 0000000..fe38b80 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:38 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./scratchpad.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './scratchpad.sh' script. + +./scratchpad.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./scratchpad.sh -noclean_files + +For more information on the script, please type './scratchpad.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/questa/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/questa/compile.do new file mode 100644 index 0000000..05b1e18 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/questa/compile.do @@ -0,0 +1,28 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xpm +vlib questa_lib/msim/blk_mem_gen_v8_4_4 +vlib questa_lib/msim/xil_defaultlib + +vmap xpm questa_lib/msim/xpm +vmap blk_mem_gen_v8_4_4 questa_lib/msim/blk_mem_gen_v8_4_4 +vmap xil_defaultlib questa_lib/msim/xil_defaultlib + +vlog -work xpm -64 -sv \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -64 \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 \ +"../../../../XUPVVH.srcs/sources_1/ip/scratchpad/sim/scratchpad.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/questa/elaborate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/questa/elaborate.do new file mode 100644 index 0000000..d4c00df --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.scratchpad xil_defaultlib.glbl -o scratchpad_opt diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/questa/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/questa/file_info.txt new file mode 100644 index 0000000..8d9f28f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/questa/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +scratchpad.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/scratchpad/sim/scratchpad.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/questa/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/questa/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/questa/scratchpad.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/questa/scratchpad.sh new file mode 100755 index 0000000..e332b90 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/questa/scratchpad.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : scratchpad.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:38 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: scratchpad.sh [-help] +# usage: scratchpad.sh [-lib_map_path] +# usage: scratchpad.sh [-noclean_files] +# usage: scratchpad.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'scratchpad.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "scratchpad.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./scratchpad.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./scratchpad.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: scratchpad.sh [-help]\n\ +Usage: scratchpad.sh [-lib_map_path]\n\ +Usage: scratchpad.sh [-reset_run]\n\ +Usage: scratchpad.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/questa/scratchpad.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/questa/scratchpad.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/questa/scratchpad.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/questa/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/questa/simulate.do new file mode 100644 index 0000000..103db82 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib scratchpad_opt + +do {wave.do} + +view wave +view structure +view signals + +do {scratchpad.udo} + +run -all + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/questa/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/questa/summary.log new file mode 100755 index 0000000..28dc68a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/questa/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [32] +Port A Write Width : [32] +Memory Depth : [1024] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 2.119075 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/questa/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/questa/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/riviera/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/riviera/README.txt new file mode 100644 index 0000000..fe38b80 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:38 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./scratchpad.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './scratchpad.sh' script. + +./scratchpad.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./scratchpad.sh -noclean_files + +For more information on the script, please type './scratchpad.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/riviera/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/riviera/compile.do new file mode 100644 index 0000000..2e925b5 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/riviera/compile.do @@ -0,0 +1,28 @@ +vlib work +vlib riviera + +vlib riviera/xpm +vlib riviera/blk_mem_gen_v8_4_4 +vlib riviera/xil_defaultlib + +vmap xpm riviera/xpm +vmap blk_mem_gen_v8_4_4 riviera/blk_mem_gen_v8_4_4 +vmap xil_defaultlib riviera/xil_defaultlib + +vlog -work xpm -sv2k12 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 \ +"../../../../XUPVVH.srcs/sources_1/ip/scratchpad/sim/scratchpad.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/riviera/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/riviera/file_info.txt new file mode 100644 index 0000000..8d9f28f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/riviera/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +scratchpad.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/scratchpad/sim/scratchpad.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/riviera/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/riviera/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/riviera/scratchpad.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/riviera/scratchpad.sh new file mode 100755 index 0000000..d7d9f58 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/riviera/scratchpad.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : scratchpad.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:38 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: scratchpad.sh [-help] +# usage: scratchpad.sh [-lib_map_path] +# usage: scratchpad.sh [-noclean_files] +# usage: scratchpad.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'scratchpad.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "scratchpad.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./scratchpad.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./scratchpad.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: scratchpad.sh [-help]\n\ +Usage: scratchpad.sh [-lib_map_path]\n\ +Usage: scratchpad.sh [-reset_run]\n\ +Usage: scratchpad.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/riviera/scratchpad.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/riviera/scratchpad.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/riviera/scratchpad.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/riviera/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/riviera/simulate.do new file mode 100644 index 0000000..c3c5ac1 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+scratchpad -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.scratchpad xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {scratchpad.udo} + +run -all + +endsim + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/riviera/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/riviera/summary.log new file mode 100755 index 0000000..28dc68a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/riviera/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [32] +Port A Write Width : [32] +Memory Depth : [1024] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 2.119075 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/riviera/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/riviera/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/vcs/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/vcs/README.txt new file mode 100644 index 0000000..fe38b80 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:38 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./scratchpad.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './scratchpad.sh' script. + +./scratchpad.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./scratchpad.sh -noclean_files + +For more information on the script, please type './scratchpad.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/vcs/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/vcs/file_info.txt new file mode 100644 index 0000000..8d9f28f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/vcs/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +scratchpad.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/scratchpad/sim/scratchpad.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/vcs/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/vcs/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/vcs/scratchpad.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/vcs/scratchpad.sh new file mode 100755 index 0000000..e75732d --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/vcs/scratchpad.sh @@ -0,0 +1,235 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : scratchpad.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:38 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: scratchpad.sh [-help] +# usage: scratchpad.sh [-lib_map_path] +# usage: scratchpad.sh [-noclean_files] +# usage: scratchpad.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'scratchpad.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "scratchpad.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + vlogan -work xpm $vlogan_opts -sverilog \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work blk_mem_gen_v8_4_4 $vlogan_opts +v2k \ + "$ref_dir/../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/scratchpad/sim/scratchpad.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.scratchpad xil_defaultlib.glbl -o scratchpad_simv +} + +# RUN_STEP: <simulate> +simulate() +{ + ./scratchpad_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./scratchpad.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/vcs" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key scratchpad_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc scratchpad_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./scratchpad.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: scratchpad.sh [-help]\n\ +Usage: scratchpad.sh [-lib_map_path]\n\ +Usage: scratchpad.sh [-reset_run]\n\ +Usage: scratchpad.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/vcs/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/vcs/simulate.do new file mode 100644 index 0000000..58afc78 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/vcs/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/vcs/summary.log new file mode 100755 index 0000000..28dc68a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/vcs/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [32] +Port A Write Width : [32] +Memory Depth : [1024] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 2.119075 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xcelium/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xcelium/README.txt new file mode 100644 index 0000000..d2dc2e7 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:38 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./scratchpad.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './scratchpad.sh' script. + +./scratchpad.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./scratchpad.sh -noclean_files + +For more information on the script, please type './scratchpad.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xcelium/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xcelium/file_info.txt new file mode 100644 index 0000000..8d9f28f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xcelium/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +scratchpad.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/scratchpad/sim/scratchpad.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xcelium/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xcelium/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xcelium/run.f b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xcelium/run.f new file mode 100644 index 0000000..801f9d7 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xcelium/run.f @@ -0,0 +1,18 @@ +-makelib xcelium_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/scratchpad/sim/scratchpad.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xcelium/scratchpad.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xcelium/scratchpad.sh new file mode 100755 index 0000000..07bcd59 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xcelium/scratchpad.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : scratchpad.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:38 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: scratchpad.sh [-help] +# usage: scratchpad.sh [-lib_map_path] +# usage: scratchpad.sh [-noclean_files] +# usage: scratchpad.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'scratchpad.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "scratchpad.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.scratchpad \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./scratchpad.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./scratchpad.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: scratchpad.sh [-help]\n\ +Usage: scratchpad.sh [-lib_map_path]\n\ +Usage: scratchpad.sh [-reset_run]\n\ +Usage: scratchpad.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xcelium/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xcelium/summary.log new file mode 100755 index 0000000..28dc68a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xcelium/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [32] +Port A Write Width : [32] +Memory Depth : [1024] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 2.119075 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xsim/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xsim/README.txt new file mode 100644 index 0000000..fe38b80 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:38 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./scratchpad.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './scratchpad.sh' script. + +./scratchpad.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./scratchpad.sh -noclean_files + +For more information on the script, please type './scratchpad.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xsim/XUPVVH.smi b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xsim/XUPVVH.smi new file mode 100644 index 0000000..7951bb9 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xsim/XUPVVH.smi @@ -0,0 +1,30 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2019.2 (64-bit) --> +<!-- SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 --> +<!-- --> +<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --> +<!-- Nov 6 2019 --> +<!-- --> +<!-- This file is generated by the software with the Tcl write_mem_info command. --> +<!-- Do not edit this file. --> + +<MemInfoSimulation Version="1" Minor="1"> + <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I"> + <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_ADDR_SPACE" ECC="NONE" Begin="0" End="98303"> + <BusBlock> + <BitLane MemType="lmb_bram_I_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303"> + <DataWidth MSB="31" LSB="0"/> + <AddressRange Begin="0" End="16383"/> + <Parity ON="false" NumBits="0"/> + <MemFile Name="bd_9f2c_lmb_bram_I_0.mem"/> + </BitLane> + </BusBlock> + </AddressSpace> + </Processor> + <Config> + <Option Name="Part" Val="xcvu37p-fsvh2892-2-e"/> + </Config> + <DRC> + <Rule Name="RDADDRCHANGE" Val="false"/> + </DRC> +</MemInfoSimulation> diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xsim/cmd.tcl b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xsim/cmd.tcl new file mode 100644 index 0000000..eef7a0f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xsim/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xsim/file_info.txt new file mode 100644 index 0000000..24669cf --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xsim/file_info.txt @@ -0,0 +1,2 @@ +scratchpad.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/scratchpad/sim/scratchpad.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xsim/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xsim/protoinst_files/bd_9f2c.protoinst b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xsim/protoinst_files/bd_9f2c.protoinst new file mode 100644 index 0000000..cf73fce --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xsim/protoinst_files/bd_9f2c.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_9f2c": { + "proto_instances": { + } + } + } +} diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xsim/scratchpad.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xsim/scratchpad.sh new file mode 100755 index 0000000..e3627ce --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xsim/scratchpad.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : scratchpad.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:38 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: scratchpad.sh [-help] +# usage: scratchpad.sh [-lib_map_path] +# usage: scratchpad.sh [-noclean_files] +# usage: scratchpad.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.2/tps/boost_1_64_0 +xvlog_opts="--relax" + + +# Script info +echo -e "scratchpad.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + xelab --relax --debug typical --mt auto -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot scratchpad xil_defaultlib.scratchpad xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + xsim scratchpad -key {Behavioral:sim_1:Functional:scratchpad} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./scratchpad.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.2/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb scratchpad.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./scratchpad.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: scratchpad.sh [-help]\n\ +Usage: scratchpad.sh [-lib_map_path]\n\ +Usage: scratchpad.sh [-reset_run]\n\ +Usage: scratchpad.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xsim/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xsim/summary.log new file mode 100755 index 0000000..28dc68a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xsim/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [32] +Port A Write Width : [32] +Memory Depth : [1024] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 2.119075 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xsim/vlog.prj b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xsim/vlog.prj new file mode 100644 index 0000000..ffc146b --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/scratchpad/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib \ +"../../../../XUPVVH.srcs/sources_1/ip/scratchpad/sim/scratchpad.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/README.txt new file mode 100644 index 0000000..3cd3d87 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +<current_working_directory>/export_sim/<simulator> + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +<simulation_top>.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +<ip-name>.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/activehdl/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/activehdl/README.txt new file mode 100644 index 0000000..120b61d --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:48 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./xdma.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './xdma.sh' script. + +./xdma.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./xdma.sh -noclean_files + +For more information on the script, please type './xdma.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/activehdl/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/activehdl/compile.do new file mode 100644 index 0000000..061823c --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/activehdl/compile.do @@ -0,0 +1,110 @@ +vlib work +vlib activehdl + +vlib activehdl/xpm +vlib activehdl/gtwizard_ultrascale_v1_7_7 +vlib activehdl/xil_defaultlib +vlib activehdl/blk_mem_gen_v8_4_4 +vlib activehdl/xdma_v4_1_4 + +vmap xpm activehdl/xpm +vmap gtwizard_ultrascale_v1_7_7 activehdl/gtwizard_ultrascale_v1_7_7 +vmap xil_defaultlib activehdl/xil_defaultlib +vmap blk_mem_gen_v8_4_4 activehdl/blk_mem_gen_v8_4_4 +vmap xdma_v4_1_4 activehdl/xdma_v4_1_4 + +vlog -work xpm -sv2k12 "+incdir+../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work gtwizard_ultrascale_v1_7_7 -v2k5 "+incdir+../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtye4_channel_wrapper.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtye4_common_wrapper.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtwizard_gtye4.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtwizard_top.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_cxs_remap.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_16k_int.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_16k.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_32k.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_4k_int.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_msix.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_rep_int.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_rep.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_tph.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gtwizard_top.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_ff_chain.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_pipeline.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_gt_channel.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_gt_common.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_clk.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_rst.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_rxeq.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_txeq.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sync_cell.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sync.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_cdr_ctrl_on_eidle.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_receiver_detect_rxterm.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_wrapper.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_top.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_init_ctrl.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pl_eq.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_vf_decode.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_vf_decode_attr.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pipe.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_seqnum_fifo.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sys_clk_gen_ps.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pcie4c_uscale_core_top.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4c_ip.v" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 "+incdir+../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_4_blk_mem_64_reg_be.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_4_blk_mem_64_noreg_be.v" \ + +vlog -work xdma_v4_1_4 -sv2k12 "+incdir+../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" \ +"../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv" \ + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/sim/xdma.sv" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/activehdl/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/activehdl/file_info.txt new file mode 100644 index 0000000..ec4e270 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/activehdl/file_info.txt @@ -0,0 +1,77 @@ +xpm_cdc.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_fifo.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_memory.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_bit_sync.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gte4_drp_arb.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_reset.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_reset_sync.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_reset_inv_sync.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_channel.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_gtye4_channel_wrapper.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtye4_channel_wrapper.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_common.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_gtye4_common_wrapper.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtye4_common_wrapper.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_gtwizard_gtye4.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtwizard_gtye4.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_gtwizard_top.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtwizard_top.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_cxs_remap.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_cxs_remap.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_16k_int.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_16k_int.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_16k.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_16k.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_32k.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_32k.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_4k_int.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_4k_int.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_msix.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_msix.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_rep_int.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_rep_int.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_rep.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_rep.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_tph.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_tph.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gtwizard_top.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gtwizard_top.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_phy_ff_chain.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_ff_chain.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_phy_pipeline.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_pipeline.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_gt_channel.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_gt_channel.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_gt_common.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_gt_common.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_phy_clk.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_clk.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_phy_rst.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_rst.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_phy_rxeq.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_rxeq.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_phy_txeq.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_txeq.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_sync_cell.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sync_cell.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_sync.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sync.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_cdr_ctrl_on_eidle.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_cdr_ctrl_on_eidle.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_receiver_detect_rxterm.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_receiver_detect_rxterm.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_phy_wrapper.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_wrapper.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_phy_top.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_top.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_init_ctrl.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_init_ctrl.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_pl_eq.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pl_eq.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_vf_decode.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_vf_decode.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_vf_decode_attr.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_vf_decode_attr.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_pipe.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pipe.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_seqnum_fifo.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_seqnum_fifo.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_sys_clk_gen_ps.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sys_clk_gen_ps.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_pcie4c_uscale_core_top.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pcie4c_uscale_core_top.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4c_ip.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_4_blk_mem_64_reg_be.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_4_blk_mem_64_reg_be.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_4_blk_mem_64_noreg_be.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_4_blk_mem_64_noreg_be.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_vl_rfs.sv,systemverilog,xdma_v4_1_4,../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap_1024.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_core_top.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/sim/xdma.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/activehdl/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/activehdl/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/activehdl/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/activehdl/simulate.do new file mode 100644 index 0000000..d586e41 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+xdma -L xpm -L gtwizard_ultrascale_v1_7_7 -L xil_defaultlib -L blk_mem_gen_v8_4_4 -L xdma_v4_1_4 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.xdma xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {xdma.udo} + +run -all + +endsim + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/activehdl/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/activehdl/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/activehdl/xdma.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/activehdl/xdma.sh new file mode 100755 index 0000000..0001e8f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/activehdl/xdma.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : xdma.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:48 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: xdma.sh [-help] +# usage: xdma.sh [-lib_map_path] +# usage: xdma.sh [-noclean_files] +# usage: xdma.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'xdma.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "xdma.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./xdma.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./xdma.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: xdma.sh [-help]\n\ +Usage: xdma.sh [-lib_map_path]\n\ +Usage: xdma.sh [-reset_run]\n\ +Usage: xdma.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/activehdl/xdma.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/activehdl/xdma.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/activehdl/xdma.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/ies/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/ies/README.txt new file mode 100644 index 0000000..f57b63c --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:48 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./xdma.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './xdma.sh' script. + +./xdma.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./xdma.sh -noclean_files + +For more information on the script, please type './xdma.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/ies/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/ies/file_info.txt new file mode 100644 index 0000000..b680091 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/ies/file_info.txt @@ -0,0 +1,77 @@ +xpm_cdc.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_fifo.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_memory.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_bit_sync.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gte4_drp_arb.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" 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+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_4_blk_mem_64_reg_be.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_4_blk_mem_64_reg_be.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_4_blk_mem_64_noreg_be.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_4_blk_mem_64_noreg_be.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_vl_rfs.sv,systemverilog,xdma_v4_1_4,../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap_1024.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_core_top.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/sim/xdma.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/ies/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/ies/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/ies/run.f b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/ies/run.f new file mode 100644 index 0000000..c0e8689 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/ies/run.f @@ -0,0 +1,96 @@ +-makelib ies_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/gtwizard_ultrascale_v1_7_7 \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtye4_channel_wrapper.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtye4_common_wrapper.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtwizard_gtye4.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtwizard_top.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_cxs_remap.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_16k_int.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_16k.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_32k.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_4k_int.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_msix.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_rep_int.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_rep.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_tph.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gtwizard_top.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_ff_chain.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_pipeline.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_gt_channel.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_gt_common.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_clk.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_rst.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_rxeq.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_txeq.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sync_cell.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sync.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_cdr_ctrl_on_eidle.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_receiver_detect_rxterm.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_wrapper.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_top.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_init_ctrl.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pl_eq.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_vf_decode.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_vf_decode_attr.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pipe.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_seqnum_fifo.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sys_clk_gen_ps.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pcie4c_uscale_core_top.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4c_ip.v" \ +-endlib +-makelib ies_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_4_blk_mem_64_reg_be.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_4_blk_mem_64_noreg_be.v" \ +-endlib +-makelib ies_lib/xdma_v4_1_4 -sv \ + "../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv" \ +-endlib +-makelib ies_lib/xil_defaultlib -sv \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/sim/xdma.sv" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/ies/xdma.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/ies/xdma.sh new file mode 100755 index 0000000..4760a80 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/ies/xdma.sh @@ -0,0 +1,179 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : xdma.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:48 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: xdma.sh [-help] +# usage: xdma.sh [-lib_map_path] +# usage: xdma.sh [-noclean_files] +# usage: xdma.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'xdma.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xpm gtwizard_ultrascale_v1_7_7 xil_defaultlib blk_mem_gen_v8_4_4 xdma_v4_1_4) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "xdma.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.xdma \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" \ + +incdir+"$ref_dir/../../../ipstatic/hdl/verilog" \ + +incdir+"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" \ + +incdir+"../../../ipstatic/hdl/verilog" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./xdma.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./xdma.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: xdma.sh [-help]\n\ +Usage: xdma.sh [-lib_map_path]\n\ +Usage: xdma.sh [-reset_run]\n\ +Usage: xdma.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/modelsim/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/modelsim/README.txt new file mode 100644 index 0000000..120b61d --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:48 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./xdma.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './xdma.sh' script. + +./xdma.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./xdma.sh -noclean_files + +For more information on the script, please type './xdma.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/modelsim/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/modelsim/compile.do new file mode 100644 index 0000000..276c38d --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/modelsim/compile.do @@ -0,0 +1,110 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xpm +vlib modelsim_lib/msim/gtwizard_ultrascale_v1_7_7 +vlib modelsim_lib/msim/xil_defaultlib +vlib modelsim_lib/msim/blk_mem_gen_v8_4_4 +vlib modelsim_lib/msim/xdma_v4_1_4 + +vmap xpm modelsim_lib/msim/xpm +vmap gtwizard_ultrascale_v1_7_7 modelsim_lib/msim/gtwizard_ultrascale_v1_7_7 +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib +vmap blk_mem_gen_v8_4_4 modelsim_lib/msim/blk_mem_gen_v8_4_4 +vmap xdma_v4_1_4 modelsim_lib/msim/xdma_v4_1_4 + +vlog -work xpm -64 -incr -sv "+incdir+../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work gtwizard_ultrascale_v1_7_7 -64 -incr "+incdir+../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v" \ + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtye4_channel_wrapper.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtye4_common_wrapper.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtwizard_gtye4.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtwizard_top.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_cxs_remap.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_16k_int.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_16k.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_32k.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_4k_int.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_msix.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_rep_int.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_rep.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_tph.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gtwizard_top.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_ff_chain.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_pipeline.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_gt_channel.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_gt_common.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_clk.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_rst.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_rxeq.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_txeq.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sync_cell.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sync.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_cdr_ctrl_on_eidle.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_receiver_detect_rxterm.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_wrapper.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_top.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_init_ctrl.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pl_eq.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_vf_decode.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_vf_decode_attr.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pipe.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_seqnum_fifo.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sys_clk_gen_ps.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pcie4c_uscale_core_top.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4c_ip.v" \ + +vlog -work blk_mem_gen_v8_4_4 -64 -incr "+incdir+../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_4_blk_mem_64_reg_be.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_4_blk_mem_64_noreg_be.v" \ + +vlog -work xdma_v4_1_4 -64 -incr -sv "+incdir+../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" \ +"../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv" \ + +vlog -work xil_defaultlib -64 -incr -sv "+incdir+../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/sim/xdma.sv" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/modelsim/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/modelsim/file_info.txt new file mode 100644 index 0000000..ec4e270 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/modelsim/file_info.txt @@ -0,0 +1,77 @@ +xpm_cdc.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_fifo.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_memory.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_bit_sync.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gte4_drp_arb.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" 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+xdma_pcie4c_ip_gt_phy_txeq.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_txeq.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_sync_cell.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sync_cell.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_sync.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sync.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_cdr_ctrl_on_eidle.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_cdr_ctrl_on_eidle.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_receiver_detect_rxterm.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_receiver_detect_rxterm.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_phy_wrapper.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_wrapper.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_phy_top.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_top.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_init_ctrl.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_init_ctrl.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_pl_eq.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pl_eq.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_vf_decode.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_vf_decode.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_vf_decode_attr.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_vf_decode_attr.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_pipe.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pipe.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_seqnum_fifo.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_seqnum_fifo.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_sys_clk_gen_ps.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sys_clk_gen_ps.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_pcie4c_uscale_core_top.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pcie4c_uscale_core_top.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4c_ip.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_4_blk_mem_64_reg_be.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_4_blk_mem_64_reg_be.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_4_blk_mem_64_noreg_be.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_4_blk_mem_64_noreg_be.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_vl_rfs.sv,systemverilog,xdma_v4_1_4,../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap_1024.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_core_top.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/sim/xdma.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/modelsim/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/modelsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/modelsim/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/modelsim/simulate.do new file mode 100644 index 0000000..b24c3dc --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xpm -L gtwizard_ultrascale_v1_7_7 -L xil_defaultlib -L blk_mem_gen_v8_4_4 -L xdma_v4_1_4 -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.xdma xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {xdma.udo} + +run -all + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/modelsim/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/modelsim/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/modelsim/xdma.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/modelsim/xdma.sh new file mode 100755 index 0000000..c449055 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/modelsim/xdma.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : xdma.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:48 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: xdma.sh [-help] +# usage: xdma.sh [-lib_map_path] +# usage: xdma.sh [-noclean_files] +# usage: xdma.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'xdma.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "xdma.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./xdma.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/modelsim" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./xdma.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: xdma.sh [-help]\n\ +Usage: xdma.sh [-lib_map_path]\n\ +Usage: xdma.sh [-reset_run]\n\ +Usage: xdma.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/modelsim/xdma.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/modelsim/xdma.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/modelsim/xdma.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/questa/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/questa/README.txt new file mode 100644 index 0000000..120b61d --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:48 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./xdma.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './xdma.sh' script. + +./xdma.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./xdma.sh -noclean_files + +For more information on the script, please type './xdma.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/questa/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/questa/compile.do new file mode 100644 index 0000000..3a83b1b --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/questa/compile.do @@ -0,0 +1,110 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xpm +vlib questa_lib/msim/gtwizard_ultrascale_v1_7_7 +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/blk_mem_gen_v8_4_4 +vlib questa_lib/msim/xdma_v4_1_4 + +vmap xpm questa_lib/msim/xpm +vmap gtwizard_ultrascale_v1_7_7 questa_lib/msim/gtwizard_ultrascale_v1_7_7 +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap blk_mem_gen_v8_4_4 questa_lib/msim/blk_mem_gen_v8_4_4 +vmap xdma_v4_1_4 questa_lib/msim/xdma_v4_1_4 + +vlog -work xpm -64 -sv "+incdir+../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work gtwizard_ultrascale_v1_7_7 -64 "+incdir+../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtye4_channel_wrapper.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtye4_common_wrapper.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtwizard_gtye4.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtwizard_top.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_cxs_remap.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_16k_int.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_16k.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_32k.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_4k_int.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_msix.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_rep_int.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_rep.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_tph.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gtwizard_top.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_ff_chain.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_pipeline.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_gt_channel.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_gt_common.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_clk.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_rst.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_rxeq.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_txeq.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sync_cell.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sync.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_cdr_ctrl_on_eidle.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_receiver_detect_rxterm.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_wrapper.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_top.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_init_ctrl.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pl_eq.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_vf_decode.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_vf_decode_attr.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pipe.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_seqnum_fifo.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sys_clk_gen_ps.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pcie4c_uscale_core_top.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4c_ip.v" \ + +vlog -work blk_mem_gen_v8_4_4 -64 "+incdir+../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_4_blk_mem_64_reg_be.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_4_blk_mem_64_noreg_be.v" \ + +vlog -work xdma_v4_1_4 -64 -sv "+incdir+../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" \ +"../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv" \ + +vlog -work xil_defaultlib -64 -sv "+incdir+../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/sim/xdma.sv" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/questa/elaborate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/questa/elaborate.do new file mode 100644 index 0000000..49b7262 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xpm -L gtwizard_ultrascale_v1_7_7 -L xil_defaultlib -L blk_mem_gen_v8_4_4 -L xdma_v4_1_4 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.xdma xil_defaultlib.glbl -o xdma_opt diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/questa/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/questa/file_info.txt new file mode 100644 index 0000000..ec4e270 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/questa/file_info.txt @@ -0,0 +1,77 @@ +xpm_cdc.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_fifo.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_memory.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_bit_sync.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gte4_drp_arb.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_reset.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" 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+xdma_pcie4c_ip_seqnum_fifo.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_seqnum_fifo.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_sys_clk_gen_ps.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sys_clk_gen_ps.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_pcie4c_uscale_core_top.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pcie4c_uscale_core_top.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4c_ip.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_4_blk_mem_64_reg_be.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_4_blk_mem_64_reg_be.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_4_blk_mem_64_noreg_be.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_4_blk_mem_64_noreg_be.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_vl_rfs.sv,systemverilog,xdma_v4_1_4,../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap_1024.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_core_top.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/sim/xdma.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/questa/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/questa/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/questa/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/questa/simulate.do new file mode 100644 index 0000000..b8e759f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib xdma_opt + +do {wave.do} + +view wave +view structure +view signals + +do {xdma.udo} + +run -all + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/questa/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/questa/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/questa/xdma.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/questa/xdma.sh new file mode 100755 index 0000000..160ab92 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/questa/xdma.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : xdma.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:48 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: xdma.sh [-help] +# usage: xdma.sh [-lib_map_path] +# usage: xdma.sh [-noclean_files] +# usage: xdma.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'xdma.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "xdma.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./xdma.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./xdma.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: xdma.sh [-help]\n\ +Usage: xdma.sh [-lib_map_path]\n\ +Usage: xdma.sh [-reset_run]\n\ +Usage: xdma.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/questa/xdma.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/questa/xdma.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/questa/xdma.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/riviera/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/riviera/README.txt new file mode 100644 index 0000000..120b61d --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:48 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./xdma.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './xdma.sh' script. + +./xdma.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./xdma.sh -noclean_files + +For more information on the script, please type './xdma.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/riviera/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/riviera/compile.do new file mode 100644 index 0000000..ab8058a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/riviera/compile.do @@ -0,0 +1,110 @@ +vlib work +vlib riviera + +vlib riviera/xpm +vlib riviera/gtwizard_ultrascale_v1_7_7 +vlib riviera/xil_defaultlib +vlib riviera/blk_mem_gen_v8_4_4 +vlib riviera/xdma_v4_1_4 + +vmap xpm riviera/xpm +vmap gtwizard_ultrascale_v1_7_7 riviera/gtwizard_ultrascale_v1_7_7 +vmap xil_defaultlib riviera/xil_defaultlib +vmap blk_mem_gen_v8_4_4 riviera/blk_mem_gen_v8_4_4 +vmap xdma_v4_1_4 riviera/xdma_v4_1_4 + +vlog -work xpm -sv2k12 "+incdir+../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work gtwizard_ultrascale_v1_7_7 -v2k5 "+incdir+../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtye4_channel_wrapper.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtye4_common_wrapper.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtwizard_gtye4.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtwizard_top.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_cxs_remap.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_16k_int.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_16k.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_32k.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_4k_int.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_msix.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_rep_int.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_rep.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_tph.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gtwizard_top.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_ff_chain.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_pipeline.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_gt_channel.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_gt_common.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_clk.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_rst.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_rxeq.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_txeq.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sync_cell.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sync.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_cdr_ctrl_on_eidle.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_receiver_detect_rxterm.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_wrapper.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_top.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_init_ctrl.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pl_eq.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_vf_decode.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_vf_decode_attr.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pipe.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_seqnum_fifo.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sys_clk_gen_ps.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pcie4c_uscale_core_top.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4c_ip.v" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 "+incdir+../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_4_blk_mem_64_reg_be.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_4_blk_mem_64_noreg_be.v" \ + +vlog -work xdma_v4_1_4 -sv2k12 "+incdir+../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" \ +"../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv" \ + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/sim/xdma.sv" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/riviera/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/riviera/file_info.txt new file mode 100644 index 0000000..ec4e270 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/riviera/file_info.txt @@ -0,0 +1,77 @@ +xpm_cdc.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_fifo.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_memory.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_bit_sync.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gte4_drp_arb.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_reset.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_reset_sync.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_reset_inv_sync.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_channel.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_gtye4_channel_wrapper.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtye4_channel_wrapper.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_common.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_gtye4_common_wrapper.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtye4_common_wrapper.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_gtwizard_gtye4.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtwizard_gtye4.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_gtwizard_top.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtwizard_top.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_cxs_remap.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_cxs_remap.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_16k_int.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_16k_int.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_16k.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_16k.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_32k.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_32k.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_4k_int.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_4k_int.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_msix.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_msix.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_rep_int.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_rep_int.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_rep.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_rep.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_tph.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_tph.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gtwizard_top.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gtwizard_top.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_phy_ff_chain.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_ff_chain.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_phy_pipeline.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_pipeline.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_gt_channel.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_gt_channel.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_gt_common.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_gt_common.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_phy_clk.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_clk.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_phy_rst.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_rst.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_phy_rxeq.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_rxeq.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_phy_txeq.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_txeq.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_sync_cell.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sync_cell.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_sync.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sync.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_cdr_ctrl_on_eidle.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_cdr_ctrl_on_eidle.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_receiver_detect_rxterm.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_receiver_detect_rxterm.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_phy_wrapper.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_wrapper.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_phy_top.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_top.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_init_ctrl.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_init_ctrl.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_pl_eq.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pl_eq.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_vf_decode.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_vf_decode.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_vf_decode_attr.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_vf_decode_attr.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_pipe.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pipe.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_seqnum_fifo.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_seqnum_fifo.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_sys_clk_gen_ps.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sys_clk_gen_ps.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_pcie4c_uscale_core_top.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pcie4c_uscale_core_top.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4c_ip.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_4_blk_mem_64_reg_be.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_4_blk_mem_64_reg_be.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_4_blk_mem_64_noreg_be.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_4_blk_mem_64_noreg_be.v,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_vl_rfs.sv,systemverilog,xdma_v4_1_4,../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap_1024.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_core_top.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/sim/xdma.sv,incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/riviera/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/riviera/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/riviera/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/riviera/simulate.do new file mode 100644 index 0000000..d586e41 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+xdma -L xpm -L gtwizard_ultrascale_v1_7_7 -L xil_defaultlib -L blk_mem_gen_v8_4_4 -L xdma_v4_1_4 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.xdma xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {xdma.udo} + +run -all + +endsim + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/riviera/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/riviera/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/riviera/xdma.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/riviera/xdma.sh new file mode 100755 index 0000000..f5abeea --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/riviera/xdma.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : xdma.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:48 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: xdma.sh [-help] +# usage: xdma.sh [-lib_map_path] +# usage: xdma.sh [-noclean_files] +# usage: xdma.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'xdma.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "xdma.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./xdma.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./xdma.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: xdma.sh [-help]\n\ +Usage: xdma.sh [-lib_map_path]\n\ +Usage: xdma.sh [-reset_run]\n\ +Usage: xdma.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/riviera/xdma.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/riviera/xdma.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/riviera/xdma.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/vcs/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/vcs/README.txt new file mode 100644 index 0000000..120b61d --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:48 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./xdma.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './xdma.sh' script. + +./xdma.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./xdma.sh -noclean_files + +For more information on the script, please type './xdma.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/vcs/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/vcs/file_info.txt new file mode 100644 index 0000000..b680091 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/vcs/file_info.txt @@ -0,0 +1,77 @@ +xpm_cdc.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_fifo.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_memory.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_bit_sync.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gte4_drp_arb.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" 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+xdma_pcie4c_ip_seqnum_fifo.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_seqnum_fifo.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_sys_clk_gen_ps.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sys_clk_gen_ps.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" 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+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_4_blk_mem_64_reg_be.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_4_blk_mem_64_reg_be.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_4_blk_mem_64_noreg_be.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_4_blk_mem_64_noreg_be.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_vl_rfs.sv,systemverilog,xdma_v4_1_4,../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap_1024.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_core_top.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/sim/xdma.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/vcs/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/vcs/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/vcs/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/vcs/simulate.do new file mode 100644 index 0000000..58afc78 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/vcs/xdma.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/vcs/xdma.sh new file mode 100755 index 0000000..42b1a19 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/vcs/xdma.sh @@ -0,0 +1,317 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : xdma.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:48 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: xdma.sh [-help] +# usage: xdma.sh [-lib_map_path] +# usage: xdma.sh [-noclean_files] +# usage: xdma.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'xdma.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xpm gtwizard_ultrascale_v1_7_7 xil_defaultlib blk_mem_gen_v8_4_4 xdma_v4_1_4) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "xdma.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + vlogan -work xpm $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" +incdir+"$ref_dir/../../../ipstatic/hdl/verilog" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work gtwizard_ultrascale_v1_7_7 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" +incdir+"$ref_dir/../../../ipstatic/hdl/verilog" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" +incdir+"$ref_dir/../../../ipstatic/hdl/verilog" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtye4_channel_wrapper.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtye4_common_wrapper.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtwizard_gtye4.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtwizard_top.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_cxs_remap.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_16k_int.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_16k.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_32k.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_4k_int.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_msix.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_rep_int.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_rep.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_tph.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gtwizard_top.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_ff_chain.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_pipeline.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_gt_channel.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_gt_common.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_clk.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_rst.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_rxeq.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_txeq.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sync_cell.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sync.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_cdr_ctrl_on_eidle.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_receiver_detect_rxterm.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_wrapper.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_top.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_init_ctrl.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pl_eq.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_vf_decode.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_vf_decode_attr.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pipe.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_seqnum_fifo.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sys_clk_gen_ps.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pcie4c_uscale_core_top.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4c_ip.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work blk_mem_gen_v8_4_4 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" +incdir+"$ref_dir/../../../ipstatic/hdl/verilog" \ + "$ref_dir/../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" +incdir+"$ref_dir/../../../ipstatic/hdl/verilog" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_4_blk_mem_64_reg_be.v" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_4_blk_mem_64_noreg_be.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xdma_v4_1_4 $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" +incdir+"$ref_dir/../../../ipstatic/hdl/verilog" \ + "$ref_dir/../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xil_defaultlib $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" +incdir+"$ref_dir/../../../ipstatic/hdl/verilog" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv" \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/sim/xdma.sv" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.xdma xil_defaultlib.glbl -o xdma_simv +} + +# RUN_STEP: <simulate> +simulate() +{ + ./xdma_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./xdma.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/vcs" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key xdma_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc xdma_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./xdma.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: xdma.sh [-help]\n\ +Usage: xdma.sh [-lib_map_path]\n\ +Usage: xdma.sh [-reset_run]\n\ +Usage: xdma.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xcelium/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xcelium/README.txt new file mode 100644 index 0000000..f57b63c --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:48 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./xdma.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './xdma.sh' script. + +./xdma.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./xdma.sh -noclean_files + +For more information on the script, please type './xdma.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xcelium/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xcelium/file_info.txt new file mode 100644 index 0000000..b680091 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xcelium/file_info.txt @@ -0,0 +1,77 @@ +xpm_cdc.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_fifo.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_memory.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_bit_sync.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gte4_drp_arb.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_reset.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v,verilog,gtwizard_ultrascale_v1_7_7,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" 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+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_4_blk_mem_64_reg_be.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_4_blk_mem_64_reg_be.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_4_blk_mem_64_noreg_be.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_4_blk_mem_64_noreg_be.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_vl_rfs.sv,systemverilog,xdma_v4_1_4,../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap_1024.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_core_top.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/sim/xdma.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xcelium/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xcelium/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xcelium/run.f b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xcelium/run.f new file mode 100644 index 0000000..42a377a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xcelium/run.f @@ -0,0 +1,96 @@ +-makelib xcelium_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/gtwizard_ultrascale_v1_7_7 \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtye4_channel_wrapper.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtye4_common_wrapper.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtwizard_gtye4.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtwizard_top.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_cxs_remap.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_16k_int.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_16k.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_32k.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_4k_int.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_msix.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_rep_int.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_rep.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_tph.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gtwizard_top.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_ff_chain.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_pipeline.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_gt_channel.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_gt_common.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_clk.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_rst.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_rxeq.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_txeq.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sync_cell.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sync.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_cdr_ctrl_on_eidle.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_receiver_detect_rxterm.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_wrapper.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_top.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_init_ctrl.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pl_eq.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_vf_decode.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_vf_decode_attr.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pipe.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_seqnum_fifo.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sys_clk_gen_ps.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pcie4c_uscale_core_top.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4c_ip.v" \ +-endlib +-makelib xcelium_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_4_blk_mem_64_reg_be.v" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_4_blk_mem_64_noreg_be.v" \ +-endlib +-makelib xcelium_lib/xdma_v4_1_4 -sv \ + "../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv" \ +-endlib +-makelib xcelium_lib/xil_defaultlib -sv \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv" \ + "../../../../XUPVVH.srcs/sources_1/ip/xdma/sim/xdma.sv" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xcelium/xdma.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xcelium/xdma.sh new file mode 100755 index 0000000..9330e16 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xcelium/xdma.sh @@ -0,0 +1,179 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : xdma.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:48 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: xdma.sh [-help] +# usage: xdma.sh [-lib_map_path] +# usage: xdma.sh [-noclean_files] +# usage: xdma.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'xdma.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xpm gtwizard_ultrascale_v1_7_7 xil_defaultlib blk_mem_gen_v8_4_4 xdma_v4_1_4) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "xdma.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.xdma \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" \ + +incdir+"$ref_dir/../../../ipstatic/hdl/verilog" \ + +incdir+"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" \ + +incdir+"../../../ipstatic/hdl/verilog" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./xdma.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./xdma.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: xdma.sh [-help]\n\ +Usage: xdma.sh [-lib_map_path]\n\ +Usage: xdma.sh [-reset_run]\n\ +Usage: xdma.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/README.txt new file mode 100644 index 0000000..120b61d --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:23:48 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./xdma.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './xdma.sh' script. + +./xdma.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./xdma.sh -noclean_files + +For more information on the script, please type './xdma.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/XUPVVH.smi b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/XUPVVH.smi new file mode 100644 index 0000000..7951bb9 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/XUPVVH.smi @@ -0,0 +1,30 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2019.2 (64-bit) --> +<!-- SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 --> +<!-- --> +<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --> +<!-- Nov 6 2019 --> +<!-- --> +<!-- This file is generated by the software with the Tcl write_mem_info command. --> +<!-- Do not edit this file. --> + +<MemInfoSimulation Version="1" Minor="1"> + <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I"> + <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_ADDR_SPACE" ECC="NONE" Begin="0" End="98303"> + <BusBlock> + <BitLane MemType="lmb_bram_I_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303"> + <DataWidth MSB="31" LSB="0"/> + <AddressRange Begin="0" End="16383"/> + <Parity ON="false" NumBits="0"/> + <MemFile Name="bd_9f2c_lmb_bram_I_0.mem"/> + </BitLane> + </BusBlock> + </AddressSpace> + </Processor> + <Config> + <Option Name="Part" Val="xcvu37p-fsvh2892-2-e"/> + </Config> + <DRC> + <Rule Name="RDADDRCHANGE" Val="false"/> + </DRC> +</MemInfoSimulation> diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/cmd.tcl b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/cmd.tcl new file mode 100644 index 0000000..eef7a0f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/file_info.txt new file mode 100644 index 0000000..f3f7702 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/file_info.txt @@ -0,0 +1,48 @@ +gtwizard_ultrascale_v1_7_gtye4_channel.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_gtye4_channel_wrapper.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtye4_channel_wrapper.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_common.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_gtye4_common_wrapper.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtye4_common_wrapper.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_gtwizard_gtye4.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtwizard_gtye4.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_gtwizard_top.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtwizard_top.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_cxs_remap.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_cxs_remap.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_16k_int.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_16k_int.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_16k.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_16k.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_32k.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_32k.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_4k_int.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_4k_int.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_msix.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_msix.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_rep_int.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_rep_int.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_rep.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_rep.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram_tph.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_tph.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_bram.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gtwizard_top.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gtwizard_top.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_phy_ff_chain.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_ff_chain.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_phy_pipeline.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_pipeline.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_gt_channel.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_gt_channel.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_gt_common.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_gt_common.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_phy_clk.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_clk.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_phy_rst.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_rst.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_phy_rxeq.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_rxeq.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_phy_txeq.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_txeq.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_sync_cell.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sync_cell.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_sync.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sync.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_cdr_ctrl_on_eidle.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_cdr_ctrl_on_eidle.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_receiver_detect_rxterm.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_receiver_detect_rxterm.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_gt_phy_wrapper.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_wrapper.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" 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+xdma_pcie4c_ip_pl_eq.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pl_eq.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_vf_decode.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_vf_decode.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_vf_decode_attr.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_vf_decode_attr.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_pipe.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pipe.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_seqnum_fifo.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_seqnum_fifo.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_sys_clk_gen_ps.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sys_clk_gen_ps.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip_pcie4c_uscale_core_top.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pcie4c_uscale_core_top.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4c_ip.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4c_ip.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_4_blk_mem_64_reg_be.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_4_blk_mem_64_reg_be.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_4_blk_mem_64_noreg_be.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_4_blk_mem_64_noreg_be.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap_1024.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_core_top.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/xdma/sim/xdma.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/protoinst_files/bd_9f2c.protoinst b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/protoinst_files/bd_9f2c.protoinst new file mode 100644 index 0000000..cf73fce --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/protoinst_files/bd_9f2c.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_9f2c": { + "proto_instances": { + } + } + } +} diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/vlog.prj b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/vlog.prj new file mode 100644 index 0000000..cfc4710 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/vlog.prj @@ -0,0 +1,54 @@ +verilog xil_defaultlib --include "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" --include "../../../ipstatic/hdl/verilog" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtye4_channel_wrapper.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtye4_common_wrapper.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtwizard_gtye4.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt_gtwizard_top.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4c_ip_gt.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_cxs_remap.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_16k_int.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_16k.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_32k.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_4k_int.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_msix.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_rep_int.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_rep.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram_tph.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_bram.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gtwizard_top.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_ff_chain.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_pipeline.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_gt_channel.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_gt_common.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_clk.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_rst.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_rxeq.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_txeq.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sync_cell.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sync.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_cdr_ctrl_on_eidle.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_receiver_detect_rxterm.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_gt_phy_wrapper.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_phy_top.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_init_ctrl.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pl_eq.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_vf_decode.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_vf_decode_attr.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pipe.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_seqnum_fifo.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_sys_clk_gen_ps.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4c_ip_pcie4c_uscale_core_top.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4c_ip.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_4_blk_mem_64_reg_be.v" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_4_blk_mem_64_noreg_be.v" \ + +sv xil_defaultlib --include "../../../../XUPVVH.srcs/sources_1/ip/xdma/ip_0/source" --include "../../../ipstatic/hdl/verilog" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv" \ +"../../../../XUPVVH.srcs/sources_1/ip/xdma/sim/xdma.sv" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/xdma.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/xdma.sh new file mode 100755 index 0000000..a28e6a4 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/xdma/xsim/xdma.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : xdma.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:23:48 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: xdma.sh [-help] +# usage: xdma.sh [-lib_map_path] +# usage: xdma.sh [-noclean_files] +# usage: xdma.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.2/tps/boost_1_64_0 +xvlog_opts="--relax" + + +# Script info +echo -e "xdma.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + xelab --relax --debug typical --mt auto -L gtwizard_ultrascale_v1_7_7 -L xil_defaultlib -L blk_mem_gen_v8_4_4 -L xdma_v4_1_4 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot xdma xil_defaultlib.xdma xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + xsim xdma -key {Behavioral:sim_1:Functional:xdma} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./xdma.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.2/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=(xil_defaultlib) + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb xdma.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./xdma.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: xdma.sh [-help]\n\ +Usage: xdma.sh [-lib_map_path]\n\ +Usage: xdma.sh [-reset_run]\n\ +Usage: xdma.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/README.txt new file mode 100644 index 0000000..3cd3d87 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +<current_working_directory>/export_sim/<simulator> + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +<simulation_top>.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +<ip-name>.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/activehdl/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/activehdl/README.txt new file mode 100644 index 0000000..7b41921 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:24:10 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./zq_calib_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './zq_calib_mem.sh' script. + +./zq_calib_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./zq_calib_mem.sh -noclean_files + +For more information on the script, please type './zq_calib_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/activehdl/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/activehdl/compile.do new file mode 100644 index 0000000..2b7526f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/activehdl/compile.do @@ -0,0 +1,28 @@ +vlib work +vlib activehdl + +vlib activehdl/xpm +vlib activehdl/blk_mem_gen_v8_4_4 +vlib activehdl/xil_defaultlib + +vmap xpm activehdl/xpm +vmap blk_mem_gen_v8_4_4 activehdl/blk_mem_gen_v8_4_4 +vmap xil_defaultlib activehdl/xil_defaultlib + +vlog -work xpm -sv2k12 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 \ +"../../../../XUPVVH.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/activehdl/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/activehdl/file_info.txt new file mode 100644 index 0000000..fe54f7a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/activehdl/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +zq_calib_mem.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/activehdl/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/activehdl/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/activehdl/pr_zq.coe b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/activehdl/pr_zq.coe new file mode 100755 index 0000000..16d563c --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/activehdl/pr_zq.coe @@ -0,0 +1,42 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001100000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/activehdl/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/activehdl/simulate.do new file mode 100644 index 0000000..ce4b423 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+zq_calib_mem -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.zq_calib_mem xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {zq_calib_mem.udo} + +run -all + +endsim + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/activehdl/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/activehdl/summary.log new file mode 100755 index 0000000..7930542 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/activehdl/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [64] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/activehdl/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/activehdl/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/activehdl/zq_calib_mem.mif b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/activehdl/zq_calib_mem.mif new file mode 100755 index 0000000..fdf3bb0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/activehdl/zq_calib_mem.mif @@ -0,0 +1,40 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010100000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001100000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/activehdl/zq_calib_mem.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/activehdl/zq_calib_mem.sh new file mode 100755 index 0000000..b2b8bb4 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/activehdl/zq_calib_mem.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : zq_calib_mem.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:24:10 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: zq_calib_mem.sh [-help] +# usage: zq_calib_mem.sh [-lib_map_path] +# usage: zq_calib_mem.sh [-noclean_files] +# usage: zq_calib_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'zq_calib_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "zq_calib_mem.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./zq_calib_mem.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./zq_calib_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: zq_calib_mem.sh [-help]\n\ +Usage: zq_calib_mem.sh [-lib_map_path]\n\ +Usage: zq_calib_mem.sh [-reset_run]\n\ +Usage: zq_calib_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/activehdl/zq_calib_mem.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/activehdl/zq_calib_mem.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/activehdl/zq_calib_mem.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/ies/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/ies/README.txt new file mode 100644 index 0000000..3860919 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:24:10 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./zq_calib_mem.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './zq_calib_mem.sh' script. + +./zq_calib_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./zq_calib_mem.sh -noclean_files + +For more information on the script, please type './zq_calib_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/ies/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/ies/file_info.txt new file mode 100644 index 0000000..fe54f7a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/ies/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +zq_calib_mem.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/ies/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/ies/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/ies/pr_zq.coe b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/ies/pr_zq.coe new file mode 100755 index 0000000..16d563c --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/ies/pr_zq.coe @@ -0,0 +1,42 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001100000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/ies/run.f b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/ies/run.f new file mode 100644 index 0000000..6e67e62 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/ies/run.f @@ -0,0 +1,18 @@ +-makelib ies_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/ies/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/ies/summary.log new file mode 100755 index 0000000..7930542 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/ies/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [64] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/ies/zq_calib_mem.mif b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/ies/zq_calib_mem.mif new file mode 100755 index 0000000..fdf3bb0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/ies/zq_calib_mem.mif @@ -0,0 +1,40 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010100000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001100000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/ies/zq_calib_mem.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/ies/zq_calib_mem.sh new file mode 100755 index 0000000..f735ec3 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/ies/zq_calib_mem.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : zq_calib_mem.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:24:10 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: zq_calib_mem.sh [-help] +# usage: zq_calib_mem.sh [-lib_map_path] +# usage: zq_calib_mem.sh [-noclean_files] +# usage: zq_calib_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'zq_calib_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "zq_calib_mem.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.zq_calib_mem \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./zq_calib_mem.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./zq_calib_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: zq_calib_mem.sh [-help]\n\ +Usage: zq_calib_mem.sh [-lib_map_path]\n\ +Usage: zq_calib_mem.sh [-reset_run]\n\ +Usage: zq_calib_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/modelsim/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/modelsim/README.txt new file mode 100644 index 0000000..7b41921 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:24:10 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./zq_calib_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './zq_calib_mem.sh' script. + +./zq_calib_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./zq_calib_mem.sh -noclean_files + +For more information on the script, please type './zq_calib_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/modelsim/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/modelsim/compile.do new file mode 100644 index 0000000..64db74e --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/modelsim/compile.do @@ -0,0 +1,28 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xpm +vlib modelsim_lib/msim/blk_mem_gen_v8_4_4 +vlib modelsim_lib/msim/xil_defaultlib + +vmap xpm modelsim_lib/msim/xpm +vmap blk_mem_gen_v8_4_4 modelsim_lib/msim/blk_mem_gen_v8_4_4 +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xpm -64 -incr -sv \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -64 -incr \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 -incr \ +"../../../../XUPVVH.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/modelsim/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/modelsim/file_info.txt new file mode 100644 index 0000000..fe54f7a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/modelsim/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +zq_calib_mem.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/modelsim/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/modelsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/modelsim/pr_zq.coe b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/modelsim/pr_zq.coe new file mode 100755 index 0000000..16d563c --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/modelsim/pr_zq.coe @@ -0,0 +1,42 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001100000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/modelsim/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/modelsim/simulate.do new file mode 100644 index 0000000..dbeafed --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.zq_calib_mem xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {zq_calib_mem.udo} + +run -all + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/modelsim/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/modelsim/summary.log new file mode 100755 index 0000000..7930542 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/modelsim/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [64] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/modelsim/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/modelsim/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/modelsim/zq_calib_mem.mif b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/modelsim/zq_calib_mem.mif new file mode 100755 index 0000000..fdf3bb0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/modelsim/zq_calib_mem.mif @@ -0,0 +1,40 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010100000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001100000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/modelsim/zq_calib_mem.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/modelsim/zq_calib_mem.sh new file mode 100755 index 0000000..f1c8e8f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/modelsim/zq_calib_mem.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : zq_calib_mem.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:24:10 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: zq_calib_mem.sh [-help] +# usage: zq_calib_mem.sh [-lib_map_path] +# usage: zq_calib_mem.sh [-noclean_files] +# usage: zq_calib_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'zq_calib_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "zq_calib_mem.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./zq_calib_mem.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/modelsim" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./zq_calib_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: zq_calib_mem.sh [-help]\n\ +Usage: zq_calib_mem.sh [-lib_map_path]\n\ +Usage: zq_calib_mem.sh [-reset_run]\n\ +Usage: zq_calib_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/modelsim/zq_calib_mem.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/modelsim/zq_calib_mem.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/modelsim/zq_calib_mem.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/README.txt new file mode 100644 index 0000000..7b41921 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:24:10 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./zq_calib_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './zq_calib_mem.sh' script. + +./zq_calib_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./zq_calib_mem.sh -noclean_files + +For more information on the script, please type './zq_calib_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/compile.do new file mode 100644 index 0000000..477f129 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/compile.do @@ -0,0 +1,28 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xpm +vlib questa_lib/msim/blk_mem_gen_v8_4_4 +vlib questa_lib/msim/xil_defaultlib + +vmap xpm questa_lib/msim/xpm +vmap blk_mem_gen_v8_4_4 questa_lib/msim/blk_mem_gen_v8_4_4 +vmap xil_defaultlib questa_lib/msim/xil_defaultlib + +vlog -work xpm -64 -sv \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -64 \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 \ +"../../../../XUPVVH.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/elaborate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/elaborate.do new file mode 100644 index 0000000..d5539e6 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.zq_calib_mem xil_defaultlib.glbl -o zq_calib_mem_opt diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/file_info.txt new file mode 100644 index 0000000..fe54f7a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +zq_calib_mem.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/pr_zq.coe b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/pr_zq.coe new file mode 100755 index 0000000..16d563c --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/pr_zq.coe @@ -0,0 +1,42 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001100000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/simulate.do new file mode 100644 index 0000000..d2a9c73 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib zq_calib_mem_opt + +do {wave.do} + +view wave +view structure +view signals + +do {zq_calib_mem.udo} + +run -all + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/summary.log new file mode 100755 index 0000000..7930542 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [64] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/zq_calib_mem.mif b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/zq_calib_mem.mif new file mode 100755 index 0000000..fdf3bb0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/zq_calib_mem.mif @@ -0,0 +1,40 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010100000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001100000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/zq_calib_mem.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/zq_calib_mem.sh new file mode 100755 index 0000000..ace7b02 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/zq_calib_mem.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : zq_calib_mem.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:24:10 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: zq_calib_mem.sh [-help] +# usage: zq_calib_mem.sh [-lib_map_path] +# usage: zq_calib_mem.sh [-noclean_files] +# usage: zq_calib_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'zq_calib_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "zq_calib_mem.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./zq_calib_mem.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./zq_calib_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: zq_calib_mem.sh [-help]\n\ +Usage: zq_calib_mem.sh [-lib_map_path]\n\ +Usage: zq_calib_mem.sh [-reset_run]\n\ +Usage: zq_calib_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/zq_calib_mem.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/zq_calib_mem.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/questa/zq_calib_mem.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/riviera/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/riviera/README.txt new file mode 100644 index 0000000..7b41921 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:24:10 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./zq_calib_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './zq_calib_mem.sh' script. + +./zq_calib_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./zq_calib_mem.sh -noclean_files + +For more information on the script, please type './zq_calib_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/riviera/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/riviera/compile.do new file mode 100644 index 0000000..c7adacb --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/riviera/compile.do @@ -0,0 +1,28 @@ +vlib work +vlib riviera + +vlib riviera/xpm +vlib riviera/blk_mem_gen_v8_4_4 +vlib riviera/xil_defaultlib + +vmap xpm riviera/xpm +vmap blk_mem_gen_v8_4_4 riviera/blk_mem_gen_v8_4_4 +vmap xil_defaultlib riviera/xil_defaultlib + +vlog -work xpm -sv2k12 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 \ +"../../../../XUPVVH.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/riviera/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/riviera/file_info.txt new file mode 100644 index 0000000..fe54f7a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/riviera/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +zq_calib_mem.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/riviera/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/riviera/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/riviera/pr_zq.coe b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/riviera/pr_zq.coe new file mode 100755 index 0000000..16d563c --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/riviera/pr_zq.coe @@ -0,0 +1,42 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001100000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/riviera/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/riviera/simulate.do new file mode 100644 index 0000000..ce4b423 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+zq_calib_mem -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.zq_calib_mem xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {zq_calib_mem.udo} + +run -all + +endsim + +quit -force diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/riviera/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/riviera/summary.log new file mode 100755 index 0000000..7930542 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/riviera/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [64] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/riviera/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/riviera/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/riviera/zq_calib_mem.mif b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/riviera/zq_calib_mem.mif new file mode 100755 index 0000000..fdf3bb0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/riviera/zq_calib_mem.mif @@ -0,0 +1,40 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010100000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001100000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/riviera/zq_calib_mem.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/riviera/zq_calib_mem.sh new file mode 100755 index 0000000..bb00e39 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/riviera/zq_calib_mem.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : zq_calib_mem.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:24:10 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: zq_calib_mem.sh [-help] +# usage: zq_calib_mem.sh [-lib_map_path] +# usage: zq_calib_mem.sh [-noclean_files] +# usage: zq_calib_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'zq_calib_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "zq_calib_mem.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./zq_calib_mem.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./zq_calib_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: zq_calib_mem.sh [-help]\n\ +Usage: zq_calib_mem.sh [-lib_map_path]\n\ +Usage: zq_calib_mem.sh [-reset_run]\n\ +Usage: zq_calib_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/riviera/zq_calib_mem.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/riviera/zq_calib_mem.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/riviera/zq_calib_mem.udo diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/vcs/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/vcs/README.txt new file mode 100644 index 0000000..7b41921 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:24:10 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./zq_calib_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './zq_calib_mem.sh' script. + +./zq_calib_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./zq_calib_mem.sh -noclean_files + +For more information on the script, please type './zq_calib_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/vcs/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/vcs/file_info.txt new file mode 100644 index 0000000..fe54f7a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/vcs/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +zq_calib_mem.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/vcs/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/vcs/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/vcs/pr_zq.coe b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/vcs/pr_zq.coe new file mode 100755 index 0000000..16d563c --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/vcs/pr_zq.coe @@ -0,0 +1,42 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001100000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/vcs/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/vcs/simulate.do new file mode 100644 index 0000000..58afc78 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/vcs/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/vcs/summary.log new file mode 100755 index 0000000..7930542 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/vcs/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [64] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/vcs/zq_calib_mem.mif b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/vcs/zq_calib_mem.mif new file mode 100755 index 0000000..fdf3bb0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/vcs/zq_calib_mem.mif @@ -0,0 +1,40 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010100000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001100000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/vcs/zq_calib_mem.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/vcs/zq_calib_mem.sh new file mode 100755 index 0000000..6161f72 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/vcs/zq_calib_mem.sh @@ -0,0 +1,235 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : zq_calib_mem.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:24:10 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: zq_calib_mem.sh [-help] +# usage: zq_calib_mem.sh [-lib_map_path] +# usage: zq_calib_mem.sh [-noclean_files] +# usage: zq_calib_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'zq_calib_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "zq_calib_mem.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + vlogan -work xpm $vlogan_opts -sverilog \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work blk_mem_gen_v8_4_4 $vlogan_opts +v2k \ + "$ref_dir/../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + "$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.zq_calib_mem xil_defaultlib.glbl -o zq_calib_mem_simv +} + +# RUN_STEP: <simulate> +simulate() +{ + ./zq_calib_mem_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./zq_calib_mem.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/vcs" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key zq_calib_mem_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc zq_calib_mem_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./zq_calib_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: zq_calib_mem.sh [-help]\n\ +Usage: zq_calib_mem.sh [-lib_map_path]\n\ +Usage: zq_calib_mem.sh [-reset_run]\n\ +Usage: zq_calib_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xcelium/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xcelium/README.txt new file mode 100644 index 0000000..3860919 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:24:10 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./zq_calib_mem.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './zq_calib_mem.sh' script. + +./zq_calib_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./zq_calib_mem.sh -noclean_files + +For more information on the script, please type './zq_calib_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xcelium/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xcelium/file_info.txt new file mode 100644 index 0000000..fe54f7a --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xcelium/file_info.txt @@ -0,0 +1,7 @@ +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +zq_calib_mem.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xcelium/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xcelium/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xcelium/pr_zq.coe b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xcelium/pr_zq.coe new file mode 100755 index 0000000..16d563c --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xcelium/pr_zq.coe @@ -0,0 +1,42 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001100000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xcelium/run.f b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xcelium/run.f new file mode 100644 index 0000000..ef8cf62 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xcelium/run.f @@ -0,0 +1,18 @@ +-makelib xcelium_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../XUPVVH.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xcelium/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xcelium/summary.log new file mode 100755 index 0000000..7930542 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xcelium/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [64] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xcelium/zq_calib_mem.mif b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xcelium/zq_calib_mem.mif new file mode 100755 index 0000000..fdf3bb0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xcelium/zq_calib_mem.mif @@ -0,0 +1,40 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010100000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001100000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xcelium/zq_calib_mem.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xcelium/zq_calib_mem.sh new file mode 100755 index 0000000..6620e25 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xcelium/zq_calib_mem.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : zq_calib_mem.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:24:10 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: zq_calib_mem.sh [-help] +# usage: zq_calib_mem.sh [-lib_map_path] +# usage: zq_calib_mem.sh [-noclean_files] +# usage: zq_calib_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'zq_calib_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "zq_calib_mem.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.zq_calib_mem \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./zq_calib_mem.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./zq_calib_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: zq_calib_mem.sh [-help]\n\ +Usage: zq_calib_mem.sh [-lib_map_path]\n\ +Usage: zq_calib_mem.sh [-reset_run]\n\ +Usage: zq_calib_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xsim/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xsim/README.txt new file mode 100644 index 0000000..7b41921 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Oct 18 14:24:10 +03 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./zq_calib_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './zq_calib_mem.sh' script. + +./zq_calib_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./zq_calib_mem.sh -noclean_files + +For more information on the script, please type './zq_calib_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xsim/XUPVVH.smi b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xsim/XUPVVH.smi new file mode 100644 index 0000000..7951bb9 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xsim/XUPVVH.smi @@ -0,0 +1,30 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2019.2 (64-bit) --> +<!-- SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 --> +<!-- --> +<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --> +<!-- Nov 6 2019 --> +<!-- --> +<!-- This file is generated by the software with the Tcl write_mem_info command. --> +<!-- Do not edit this file. --> + +<MemInfoSimulation Version="1" Minor="1"> + <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I"> + <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_ADDR_SPACE" ECC="NONE" Begin="0" End="98303"> + <BusBlock> + <BitLane MemType="lmb_bram_I_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303"> + <DataWidth MSB="31" LSB="0"/> + <AddressRange Begin="0" End="16383"/> + <Parity ON="false" NumBits="0"/> + <MemFile Name="bd_9f2c_lmb_bram_I_0.mem"/> + </BitLane> + </BusBlock> + </AddressSpace> + </Processor> + <Config> + <Option Name="Part" Val="xcvu37p-fsvh2892-2-e"/> + </Config> + <DRC> + <Rule Name="RDADDRCHANGE" Val="false"/> + </DRC> +</MemInfoSimulation> diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xsim/cmd.tcl b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xsim/cmd.tcl new file mode 100644 index 0000000..eef7a0f --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xsim/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xsim/file_info.txt new file mode 100644 index 0000000..cd59710 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xsim/file_info.txt @@ -0,0 +1,2 @@ +zq_calib_mem.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xsim/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xsim/pr_zq.coe b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xsim/pr_zq.coe new file mode 100755 index 0000000..16d563c --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xsim/pr_zq.coe @@ -0,0 +1,42 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001100000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xsim/protoinst_files/bd_9f2c.protoinst b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xsim/protoinst_files/bd_9f2c.protoinst new file mode 100644 index 0000000..cf73fce --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xsim/protoinst_files/bd_9f2c.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_9f2c": { + "proto_instances": { + } + } + } +} diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xsim/summary.log b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xsim/summary.log new file mode 100755 index 0000000..7930542 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xsim/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [64] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xsim/vlog.prj b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xsim/vlog.prj new file mode 100644 index 0000000..d298e23 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib \ +"../../../../XUPVVH.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xsim/zq_calib_mem.mif b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xsim/zq_calib_mem.mif new file mode 100755 index 0000000..fdf3bb0 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xsim/zq_calib_mem.mif @@ -0,0 +1,40 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010100000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001100000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 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0000000..5c12d34 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/zq_calib_mem/xsim/zq_calib_mem.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.2 (64-bit) +# +# Filename : zq_calib_mem.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Oct 18 14:24:10 +03 2020 +# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: zq_calib_mem.sh [-help] +# usage: zq_calib_mem.sh [-lib_map_path] +# usage: zq_calib_mem.sh [-noclean_files] +# usage: zq_calib_mem.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.2/tps/boost_1_64_0 +xvlog_opts="--relax" + + +# Script info +echo -e "zq_calib_mem.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + xelab --relax --debug typical --mt auto -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot zq_calib_mem xil_defaultlib.zq_calib_mem xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + xsim zq_calib_mem -key {Behavioral:sim_1:Functional:zq_calib_mem} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./zq_calib_mem.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.2/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb zq_calib_mem.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./zq_calib_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: zq_calib_mem.sh [-help]\n\ +Usage: zq_calib_mem.sh [-lib_map_path]\n\ +Usage: zq_calib_mem.sh [-reset_run]\n\ +Usage: zq_calib_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 |