| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | README.txt | 2155 | logstatsplainblame |
| -rw-r--r-- | compile.do | 9362 | logstatsplainblame |
| -rw-r--r-- | file_info.txt | 37695 | logstatsplainblame |
| -rw-r--r-- | glbl.v | 1762 | logstatsplainblame |
| -rwxr-xr-x | phy_ddr4_udimm.h | 15889 | logstatsplainblame |
| -rwxr-xr-x | phy_ddr4_udimm.sh | 4968 | logstatsplainblame |
| -rw-r--r-- | phy_ddr4_udimm.udo | 0 | logstatsplainblame |
| -rwxr-xr-x | phy_ddr4_udimm_sc.h | 3058 | logstatsplainblame |
| -rwxr-xr-x | sim_ddr_v2_0.h | 9286 | logstatsplainblame |
| -rw-r--r-- | simulate.do | 467 | logstatsplainblame |
| -rw-r--r-- | wave.do | 30 | logstatsplainblame |
 |
index : dram-bender.git | |
| Experimental FPGA-based DRAM memory controller |
| aboutsummaryrefslogtreecommitdiffstats |