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+# TurboSwap
+
+**FPGA-based SDIO Interface Memory Expansion Module for Smartphones**
+
+TurboSwap is a flexible PCB module that connects to smartphones via the SDIO interface, providing memory expansion through switchable access to either external Micro-SD cards or high-speed PSRAM (LPDDR4X). At its core is a Lattice iCE40UP3K FPGA that routes SDIO commands dynamically between the two memory types based on memory map.
+
+Currently only XZ2C is supported.
+
+![photo](photo.png)
+
+## Installation
+
+1. **Flex PCB Soldering**:
+   - Align the 14-pin Micro-SD edge connector with your smartphone's SDIO interface
+   - Use low-temperature solder (SAC305 recommended) to prevent damage to the flexible PCB substrate
+   - Apply gentle, even pressure during soldering to ensure proper pin alignment
+   - Connect the Micro-SD edge connector pins: CLK, CMD, DAT0-DAT3, VCC, VSS, WP, and reserved pins
+
+2. **Power Connection**:
+   - The module draws power directly from the smartphone's SDIO interface (3.3V VCC)
+   - Internal AP2112K LDO regulators generate stable 1.2V for the FPGA core
+   - No external power supply needed - operates entirely from SDIO bus power
+
+3. **Memory Configuration**:
+   - Insert Micro-SD card into the external card reader slot
+   - For PSRAM-only operation, ensure SD card is either removed or disabled via FPGA configuration
+
+## Structure
+
+### Hardware Architecture
+
+- **FPGA**: Lattice iCE40UP3K (SG48 package) - Memory routing controller
+- **Memory Subsystem**: Kingston 32EM16-M4CTX29-8AD11 (32GB eMMC + 16Gb LPDDR4X)
+  - eMMC interface for block storage (like SD card)
+  - LPDDR4X interface for high-speed RAM-like operations
+- **Connectors**:
+  - J1: Micro-SD Edge Connector (14-pin SDIO to smartphone)
+  - J2: µSD Card Reader (external storage expansion)
+  - J3: Debug/Programming Header (2×4 pins for FPGA configuration)
+- **Power Management**: AP2112K LDO regulators for clean 3.3V→1.2V conversion
+- **Signal Integrity**: 10kΩ pull-ups on SDIO data lines, 22Ω series termination on high-speed traces
+
+### FPGA Design (Verilog HDL)
+
+Core modules implementing memory routing:
+- `turbo_top.v`: Main switching fabric and control logic
+- `sdio_to_spi.v`: SDIO protocol to SPI command translation
+- `memory_router.v`: Dynamic routing between eMMC and LPDDR4X interfaces
+- `cache_controller.v`: 32KB direct-mapped cache with LRU replacement
+- `clock_divider.v`: Clock domain crossing and timing optimization
+- `fifo_buffer.v`: Dual-clock FIFOs for rate matching between interfaces
+
+## Performance
+
+### Memory Specifications
+
+| Component | Specification | Benefit |
+|-----------|---------------|---------|
+| **SD Card Interface** | SDIO High-Speed (50MHz), up to 25MB/s sequential | Traditional storage compatibility |
+| **PSRAM Interface** | LPDDR4X @ 3200 Mbps, 32-bit bus | RAM-like performance on SDIO bus |
+| **eMMC Storage** | 32GB NAND Flash, eMMC 5.1 compatible | Non-volatile storage for persistent data |
+| **Hybrid Performance** | Mixed read/write optimization | Best of both worlds: speed + persistence |
+
+### Latency Comparison
+
+| Operation | TurboSwap (PSRAM) | SD Card Standard | Improvement |
+|-----------|-------------------|------------------|-------------|
+| **Random Read** | 35-96ns | 100µs - 1ms | 1000-30000× faster |
+| **Sequential Read (4KB)** | ~12µs | ~100µs | 8× faster |
+| **Random Write** | Cache write-back | 100µs - 10ms | Depends on cache policy |
+| **Sequential Write** | Batched to SD | 15-20MB/s | Similar sustained throughput |
+| **Access Granularity** | Byte-addressable | 512B blocks | Finer granularity |
+
+## License
+
+TurboSwap is open-source hardware released under the **CERN Open Hardware License Version 2 - Strongly Reciprocal (CERN-OHL-S)**.
+
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