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2021-02-11Corrected photo image size for previewHEADmasterLeonard Kugis-1/+1
2021-02-11Added READMELeonard Kugis-0/+77
2021-02-11Implemented Makefile for convenienceLeonard Kugis-0/+83
2021-02-11Reimplemented all HDL filesLeonard Kugis-0/+988
2021-02-10Added lib to gitignoreLeonard Kugis-1/+1
2021-02-07Add remaining SDIO data nets for complete interfaceLeonard Kugis-0/+3
2021-02-07Add .gitignore for libraries and temporary filesLeonard Kugis-0/+3
2021-02-06Update project file with complete design settingsLeonard Kugis-1/+626
2021-02-05Complete main schematic with all connectionsLeonard Kugis-37/+1330
2021-02-05Complete PCB layout with all components and routingLeonard Kugis-24/+8003
2021-02-04Route SD_DAT0 signal lineLeonard Kugis-0/+3
2021-02-04Route SD_CMD signal with via for layer transitionLeonard Kugis-0/+3
2021-02-03Add redesigned SDIO interface schematicLeonard Kugis-0/+271
2021-02-03Route SD_CLK signal with via for layer changeLeonard Kugis-0/+3
2021-02-02Add GND routing on bottom layerLeonard Kugis-0/+2
2021-02-02Route VCC3V3 power trace between componentsLeonard Kugis-0/+2
2021-02-01Add SDIO signal nets for memory interfaceLeonard Kugis-0/+3
2021-02-01Add SD card reader for external storageLeonard Kugis-0/+6
2021-01-31Remove SDIO interface schematic for redesignLeonard Kugis-271/+0
2021-01-30Complete main schematic bracketsLeonard Kugis-0/+1
2021-01-30Add VCC3V3 power connectionLeonard Kugis-0/+5
2021-01-29Add Micro-SD edge connector J1Leonard Kugis-0/+6
2021-01-29Add second QSPI Flash U3 for redundancyLeonard Kugis-0/+6
2021-01-28Add QSPI Flash U2 componentLeonard Kugis-0/+6
2021-01-28Define power nets VCC3V3 and GNDLeonard Kugis-0/+3
2021-01-27Add QSPI Flash memory symbolsLeonard Kugis-0/+1
2021-01-27Add FPGA symbol to schematicLeonard Kugis-0/+5
2021-01-26Place FPGA component on PCBLeonard Kugis-0/+1
2021-01-26Start fresh main schematicLeonard Kugis-0/+1
2021-01-25Remove main schematic due to wiring errorsLeonard Kugis-1330/+0
2021-01-25Set PCB design rulesLeonard Kugis-0/+1
2021-01-25Define PCB layersLeonard Kugis-0/+1
2021-01-24Add SDIO interface with connector and pull-up resistorsLeonard Kugis-1/+271
2021-01-24Initialize PCB layout with basic parametersLeonard Kugis-1/+2
2021-01-23Create SDIO interface schematic stubLeonard Kugis-0/+1
2021-01-23Add complete power schematic with voltage regulatorsLeonard Kugis-2/+296
2021-01-22Add complete main schematic with FPGA and componentsLeonard Kugis-1/+1296
2021-01-22Initialize PCB layout fileLeonard Kugis-0/+1
2021-01-22Extend power schematic with basic structureLeonard Kugis-0/+1
2021-01-21Add power schematic stubLeonard Kugis-0/+1
2021-01-21Start main schematic with root sheetLeonard Kugis-0/+35
2021-01-20Create initial project fileLeonard Kugis-0/+1
2021-01-20Add component libraries (symbols and footprints)Leonard Kugis-0/+27042
2021-01-20Add symbol library tableLeonard Kugis-0/+13
2021-01-20Add initial footprint library tableLeonard Kugis-0/+13
generated by cgit v1.2.3 (git 2.39.1) at 2026-02-20 22:20:08 +0000