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Diffstat (limited to 'projects/U200/U200.ip_user_files/ip')
48 files changed, 3490 insertions, 0 deletions
diff --git a/projects/U200/U200.ip_user_files/ip/axis_clock_converter/axis_clock_converter.veo b/projects/U200/U200.ip_user_files/ip/axis_clock_converter/axis_clock_converter.veo new file mode 100755 index 0000000..40c827c --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/axis_clock_converter/axis_clock_converter.veo @@ -0,0 +1,78 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:axis_clock_converter:1.1 +// IP Revision: 23 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +axis_clock_converter your_instance_name ( + .s_axis_aresetn(s_axis_aresetn), // input wire s_axis_aresetn + .m_axis_aresetn(m_axis_aresetn), // input wire m_axis_aresetn + .s_axis_aclk(s_axis_aclk), // input wire s_axis_aclk + .s_axis_tvalid(s_axis_tvalid), // input wire s_axis_tvalid + .s_axis_tready(s_axis_tready), // output wire s_axis_tready + .s_axis_tdata(s_axis_tdata), // input wire [255 : 0] s_axis_tdata + .s_axis_tkeep(s_axis_tkeep), // input wire [31 : 0] s_axis_tkeep + .s_axis_tlast(s_axis_tlast), // input wire s_axis_tlast + .m_axis_aclk(m_axis_aclk), // input wire m_axis_aclk + .m_axis_tvalid(m_axis_tvalid), // output wire m_axis_tvalid + .m_axis_tready(m_axis_tready), // input wire m_axis_tready + .m_axis_tdata(m_axis_tdata), // output wire [255 : 0] m_axis_tdata + .m_axis_tkeep(m_axis_tkeep), // output wire [31 : 0] m_axis_tkeep + .m_axis_tlast(m_axis_tlast) // output wire m_axis_tlast +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file axis_clock_converter.v when simulating +// the core, axis_clock_converter. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U200/U200.ip_user_files/ip/axis_clock_converter/axis_clock_converter.vho b/projects/U200/U200.ip_user_files/ip/axis_clock_converter/axis_clock_converter.vho new file mode 100755 index 0000000..bd502d6 --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/axis_clock_converter/axis_clock_converter.vho @@ -0,0 +1,101 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:axis_clock_converter:1.1 +-- IP Revision: 23 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axis_clock_converter + PORT ( + s_axis_aresetn : IN STD_LOGIC; + m_axis_aresetn : IN STD_LOGIC; + s_axis_aclk : IN STD_LOGIC; + s_axis_tvalid : IN STD_LOGIC; + s_axis_tready : OUT STD_LOGIC; + s_axis_tdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + s_axis_tkeep : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axis_tlast : IN STD_LOGIC; + m_axis_aclk : IN STD_LOGIC; + m_axis_tvalid : OUT STD_LOGIC; + m_axis_tready : IN STD_LOGIC; + m_axis_tdata : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + m_axis_tkeep : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axis_tlast : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axis_clock_converter + PORT MAP ( + s_axis_aresetn => s_axis_aresetn, + m_axis_aresetn => m_axis_aresetn, + s_axis_aclk => s_axis_aclk, + s_axis_tvalid => s_axis_tvalid, + s_axis_tready => s_axis_tready, + s_axis_tdata => s_axis_tdata, + s_axis_tkeep => s_axis_tkeep, + s_axis_tlast => s_axis_tlast, + m_axis_aclk => m_axis_aclk, + m_axis_tvalid => m_axis_tvalid, + m_axis_tready => m_axis_tready, + m_axis_tdata => m_axis_tdata, + m_axis_tkeep => m_axis_tkeep, + m_axis_tlast => m_axis_tlast + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axis_clock_converter.vhd when simulating +-- the core, axis_clock_converter. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U200/U200.ip_user_files/ip/axis_clock_converter/axis_clock_converter_stub.v b/projects/U200/U200.ip_user_files/ip/axis_clock_converter/axis_clock_converter_stub.v new file mode 100644 index 0000000..e808aed --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/axis_clock_converter/axis_clock_converter_stub.v @@ -0,0 +1,35 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Tue Mar 8 14:24:15 2022 +// Host : machine running 64-bit Ubuntu 20.04.4 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/axis_clock_converter_1/axis_clock_converter_stub.v +// Design : axis_clock_converter +// Purpose : Stub declaration of top-level module interface +// Device : xcu200-fsgd2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "axis_clock_converter_v1_1_23_axis_clock_converter,Vivado 2020.2" *) +module axis_clock_converter(s_axis_aresetn, m_axis_aresetn, s_axis_aclk, + s_axis_tvalid, s_axis_tready, s_axis_tdata, s_axis_tkeep, s_axis_tlast, m_axis_aclk, + m_axis_tvalid, m_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tlast) +/* synthesis syn_black_box black_box_pad_pin="s_axis_aresetn,m_axis_aresetn,s_axis_aclk,s_axis_tvalid,s_axis_tready,s_axis_tdata[255:0],s_axis_tkeep[31:0],s_axis_tlast,m_axis_aclk,m_axis_tvalid,m_axis_tready,m_axis_tdata[255:0],m_axis_tkeep[31:0],m_axis_tlast" */; + input s_axis_aresetn; + input m_axis_aresetn; + input s_axis_aclk; + input s_axis_tvalid; + output s_axis_tready; + input [255:0]s_axis_tdata; + input [31:0]s_axis_tkeep; + input s_axis_tlast; + input m_axis_aclk; + output m_axis_tvalid; + input m_axis_tready; + output [255:0]m_axis_tdata; + output [31:0]m_axis_tkeep; + output m_axis_tlast; +endmodule diff --git a/projects/U200/U200.ip_user_files/ip/axis_clock_converter/axis_clock_converter_stub.vhdl b/projects/U200/U200.ip_user_files/ip/axis_clock_converter/axis_clock_converter_stub.vhdl new file mode 100644 index 0000000..8c8a8ae --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/axis_clock_converter/axis_clock_converter_stub.vhdl @@ -0,0 +1,43 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Tue Mar 8 14:24:15 2022 +-- Host : machine running 64-bit Ubuntu 20.04.4 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/axis_clock_converter_1/axis_clock_converter_stub.vhdl +-- Design : axis_clock_converter +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu200-fsgd2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity axis_clock_converter is + Port ( + s_axis_aresetn : in STD_LOGIC; + m_axis_aresetn : in STD_LOGIC; + s_axis_aclk : in STD_LOGIC; + s_axis_tvalid : in STD_LOGIC; + s_axis_tready : out STD_LOGIC; + s_axis_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 ); + s_axis_tkeep : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axis_tlast : in STD_LOGIC; + m_axis_aclk : in STD_LOGIC; + m_axis_tvalid : out STD_LOGIC; + m_axis_tready : in STD_LOGIC; + m_axis_tdata : out STD_LOGIC_VECTOR ( 255 downto 0 ); + m_axis_tkeep : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axis_tlast : out STD_LOGIC + ); + +end axis_clock_converter; + +architecture stub of axis_clock_converter is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "s_axis_aresetn,m_axis_aresetn,s_axis_aclk,s_axis_tvalid,s_axis_tready,s_axis_tdata[255:0],s_axis_tkeep[31:0],s_axis_tlast,m_axis_aclk,m_axis_tvalid,m_axis_tready,m_axis_tdata[255:0],m_axis_tkeep[31:0],m_axis_tlast"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "axis_clock_converter_v1_1_23_axis_clock_converter,Vivado 2020.2"; +begin +end; diff --git a/projects/U200/U200.ip_user_files/ip/instr_blk_mem/instr_blk_mem.veo b/projects/U200/U200.ip_user_files/ip/instr_blk_mem/instr_blk_mem.veo new file mode 100755 index 0000000..7b3bf48 --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/instr_blk_mem/instr_blk_mem.veo @@ -0,0 +1,70 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +// IP Revision: 4 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +instr_blk_mem your_instance_name ( + .clka(clka), // input wire clka + .ena(ena), // input wire ena + .wea(wea), // input wire [0 : 0] wea + .addra(addra), // input wire [10 : 0] addra + .dina(dina), // input wire [63 : 0] dina + .douta(douta) // output wire [63 : 0] douta +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file instr_blk_mem.v when simulating +// the core, instr_blk_mem. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U200/U200.ip_user_files/ip/instr_blk_mem/instr_blk_mem.vho b/projects/U200/U200.ip_user_files/ip/instr_blk_mem/instr_blk_mem.vho new file mode 100755 index 0000000..53ad1c8 --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/instr_blk_mem/instr_blk_mem.vho @@ -0,0 +1,85 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +-- IP Revision: 4 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT instr_blk_mem + PORT ( + clka : IN STD_LOGIC; + ena : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : instr_blk_mem + PORT MAP ( + clka => clka, + ena => ena, + wea => wea, + addra => addra, + dina => dina, + douta => douta + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file instr_blk_mem.vhd when simulating +-- the core, instr_blk_mem. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U200/U200.ip_user_files/ip/instr_blk_mem/instr_blk_mem_stub.v b/projects/U200/U200.ip_user_files/ip/instr_blk_mem/instr_blk_mem_stub.v new file mode 100644 index 0000000..a5c7dc9 --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/instr_blk_mem/instr_blk_mem_stub.v @@ -0,0 +1,25 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Tue Mar 8 14:24:42 2022 +// Host : machine running 64-bit Ubuntu 20.04.4 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem_stub.v +// Design : instr_blk_mem +// Purpose : Stub declaration of top-level module interface +// Device : xcu200-fsgd2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2020.2" *) +module instr_blk_mem(clka, ena, wea, addra, dina, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[10:0],dina[63:0],douta[63:0]" */; + input clka; + input ena; + input [0:0]wea; + input [10:0]addra; + input [63:0]dina; + output [63:0]douta; +endmodule diff --git a/projects/U200/U200.ip_user_files/ip/instr_blk_mem/instr_blk_mem_stub.vhdl b/projects/U200/U200.ip_user_files/ip/instr_blk_mem/instr_blk_mem_stub.vhdl new file mode 100644 index 0000000..1814cbd --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/instr_blk_mem/instr_blk_mem_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Tue Mar 8 14:24:43 2022 +-- Host : machine running 64-bit Ubuntu 20.04.4 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem_stub.vhdl +-- Design : instr_blk_mem +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu200-fsgd2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity instr_blk_mem is + Port ( + clka : in STD_LOGIC; + ena : in STD_LOGIC; + wea : in STD_LOGIC_VECTOR ( 0 to 0 ); + addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); + dina : in STD_LOGIC_VECTOR ( 63 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 63 downto 0 ) + ); + +end instr_blk_mem; + +architecture stub of instr_blk_mem is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[10:0],dina[63:0],douta[63:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2020.2"; +begin +end; diff --git a/projects/U200/U200.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim.veo b/projects/U200/U200.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim.veo new file mode 100755 index 0000000..ec5eb2b --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim.veo @@ -0,0 +1,70 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +// IP Revision: 4 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +instr_blk_mem_sim your_instance_name ( + .clka(clka), // input wire clka + .ena(ena), // input wire ena + .wea(wea), // input wire [0 : 0] wea + .addra(addra), // input wire [9 : 0] addra + .dina(dina), // input wire [63 : 0] dina + .douta(douta) // output wire [63 : 0] douta +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file instr_blk_mem_sim.v when simulating +// the core, instr_blk_mem_sim. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U200/U200.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim.vho b/projects/U200/U200.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim.vho new file mode 100755 index 0000000..ae225e5 --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim.vho @@ -0,0 +1,85 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +-- IP Revision: 4 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT instr_blk_mem_sim + PORT ( + clka : IN STD_LOGIC; + ena : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : instr_blk_mem_sim + PORT MAP ( + clka => clka, + ena => ena, + wea => wea, + addra => addra, + dina => dina, + douta => douta + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file instr_blk_mem_sim.vhd when simulating +-- the core, instr_blk_mem_sim. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U200/U200.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim_stub.v b/projects/U200/U200.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim_stub.v new file mode 100644 index 0000000..9fbadc8 --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim_stub.v @@ -0,0 +1,25 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Tue Mar 8 14:24:43 2022 +// Host : machine running 64-bit Ubuntu 20.04.4 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/instr_blk_mem_sim/instr_blk_mem_sim_stub.v +// Design : instr_blk_mem_sim +// Purpose : Stub declaration of top-level module interface +// Device : xcu200-fsgd2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2020.2" *) +module instr_blk_mem_sim(clka, ena, wea, addra, dina, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[9:0],dina[63:0],douta[63:0]" */; + input clka; + input ena; + input [0:0]wea; + input [9:0]addra; + input [63:0]dina; + output [63:0]douta; +endmodule diff --git a/projects/U200/U200.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim_stub.vhdl b/projects/U200/U200.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim_stub.vhdl new file mode 100644 index 0000000..12c1912 --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Tue Mar 8 14:24:43 2022 +-- Host : machine running 64-bit Ubuntu 20.04.4 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/instr_blk_mem_sim/instr_blk_mem_sim_stub.vhdl +-- Design : instr_blk_mem_sim +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu200-fsgd2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity instr_blk_mem_sim is + Port ( + clka : in STD_LOGIC; + ena : in STD_LOGIC; + wea : in STD_LOGIC_VECTOR ( 0 to 0 ); + addra : in STD_LOGIC_VECTOR ( 9 downto 0 ); + dina : in STD_LOGIC_VECTOR ( 63 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 63 downto 0 ) + ); + +end instr_blk_mem_sim; + +architecture stub of instr_blk_mem_sim is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[9:0],dina[63:0],douta[63:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2020.2"; +begin +end; diff --git a/projects/U200/U200.ip_user_files/ip/phy_ddr4/phy_ddr4.veo b/projects/U200/U200.ip_user_files/ip/phy_ddr4/phy_ddr4.veo new file mode 100755 index 0000000..10d8dbe --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/phy_ddr4/phy_ddr4.veo @@ -0,0 +1,116 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:ddr4:2.2 +// IP Revision: 10 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +phy_ddr4 your_instance_name ( + .c0_init_calib_complete(c0_init_calib_complete), // output wire c0_init_calib_complete + .dbg_clk(dbg_clk), // output wire dbg_clk + .c0_sys_clk_p(c0_sys_clk_p), // input wire c0_sys_clk_p + .c0_sys_clk_n(c0_sys_clk_n), // input wire c0_sys_clk_n + .dbg_bus(dbg_bus), // output wire [511 : 0] dbg_bus + .c0_ddr4_parity(c0_ddr4_parity), // output wire c0_ddr4_parity + .c0_ddr4_ui_clk(c0_ddr4_ui_clk), // output wire c0_ddr4_ui_clk + .c0_ddr4_ui_clk_sync_rst(c0_ddr4_ui_clk_sync_rst), // output wire c0_ddr4_ui_clk_sync_rst + .addn_ui_clkout1(addn_ui_clkout1), // output wire addn_ui_clkout1 + .sys_rst(sys_rst), // input wire sys_rst + .rdDataEn(rdDataEn), // output wire [0 : 0] rdDataEn + .rdDataEnd(rdDataEnd), // output wire [0 : 0] rdDataEnd + .per_rd_done(per_rd_done), // output wire [0 : 0] per_rd_done + .rmw_rd_done(rmw_rd_done), // output wire [0 : 0] rmw_rd_done + .wrDataEn(wrDataEn), // output wire [0 : 0] wrDataEn + .mc_ACT_n(mc_ACT_n), // input wire [7 : 0] mc_ACT_n + .mcCasSlot(mcCasSlot), // input wire [1 : 0] mcCasSlot + .mcCasSlot2(mcCasSlot2), // input wire [0 : 0] mcCasSlot2 + .mcRdCAS(mcRdCAS), // input wire [0 : 0] mcRdCAS + .mcWrCAS(mcWrCAS), // input wire [0 : 0] mcWrCAS + .winInjTxn(winInjTxn), // input wire [0 : 0] winInjTxn + .winRmw(winRmw), // input wire [0 : 0] winRmw + .gt_data_ready(gt_data_ready), // input wire gt_data_ready + .winRank(winRank), // input wire [1 : 0] winRank + .tCWL(tCWL), // output wire [5 : 0] tCWL + .wrData(wrData), // input wire [575 : 0] wrData + .rdData(rdData), // output wire [575 : 0] rdData + .mc_ADR(mc_ADR), // input wire [143 : 0] mc_ADR + .mc_BA(mc_BA), // input wire [15 : 0] mc_BA + .mc_CKE(mc_CKE), // input wire [7 : 0] mc_CKE + .mc_CS_n(mc_CS_n), // input wire [7 : 0] mc_CS_n + .mc_ODT(mc_ODT), // input wire [7 : 0] mc_ODT + .dBufAdr(dBufAdr), // input wire [4 : 0] dBufAdr + .rdDataAddr(rdDataAddr), // output wire [4 : 0] rdDataAddr + .wrDataAddr(wrDataAddr), // output wire [4 : 0] wrDataAddr + .winBuf(winBuf), // input wire [4 : 0] winBuf + .ddr4_act_n(ddr4_act_n), // output wire ddr4_act_n + .ddr4_adr(ddr4_adr), // output wire [17 : 0] ddr4_adr + .ddr4_ba(ddr4_ba), // output wire [1 : 0] ddr4_ba + .ddr4_bg(ddr4_bg), // output wire [1 : 0] ddr4_bg + .ddr4_par(ddr4_par), // output wire ddr4_par + .ddr4_cke(ddr4_cke), // output wire [0 : 0] ddr4_cke + .ddr4_odt(ddr4_odt), // output wire [0 : 0] ddr4_odt + .ddr4_cs_n(ddr4_cs_n), // output wire [0 : 0] ddr4_cs_n + .ddr4_ck_t(ddr4_ck_t), // output wire ddr4_ck_t + .ddr4_ck_c(ddr4_ck_c), // output wire ddr4_ck_c + .ddr4_reset_n(ddr4_reset_n), // output wire ddr4_reset_n + .ddr4_parity(ddr4_parity), // output wire ddr4_parity + .ddr4_dq(ddr4_dq), // inout wire [71 : 0] ddr4_dq + .ddr4_dqs_c(ddr4_dqs_c), // inout wire [17 : 0] ddr4_dqs_c + .ddr4_dqs_t(ddr4_dqs_t), // inout wire [17 : 0] ddr4_dqs_t + .mc_BG(mc_BG) // input wire [15 : 0] mc_BG +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file phy_ddr4.v when simulating +// the core, phy_ddr4. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U200/U200.ip_user_files/ip/phy_ddr4/phy_ddr4.vho b/projects/U200/U200.ip_user_files/ip/phy_ddr4/phy_ddr4.vho new file mode 100755 index 0000000..24c61fa --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/phy_ddr4/phy_ddr4.vho @@ -0,0 +1,177 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:ddr4:2.2 +-- IP Revision: 10 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT phy_ddr4 + PORT ( + c0_init_calib_complete : OUT STD_LOGIC; + dbg_clk : OUT STD_LOGIC; + c0_sys_clk_p : IN STD_LOGIC; + c0_sys_clk_n : IN STD_LOGIC; + dbg_bus : OUT STD_LOGIC_VECTOR(511 DOWNTO 0); + c0_ddr4_parity : OUT STD_LOGIC; + c0_ddr4_ui_clk : OUT STD_LOGIC; + c0_ddr4_ui_clk_sync_rst : OUT STD_LOGIC; + addn_ui_clkout1 : OUT STD_LOGIC; + sys_rst : IN STD_LOGIC; + rdDataEn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + rdDataEnd : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + per_rd_done : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + rmw_rd_done : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + wrDataEn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + mc_ACT_n : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + mcCasSlot : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + mcCasSlot2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + mcRdCAS : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + mcWrCAS : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + winInjTxn : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + winRmw : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_data_ready : IN STD_LOGIC; + winRank : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + tCWL : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + wrData : IN STD_LOGIC_VECTOR(575 DOWNTO 0); + rdData : OUT STD_LOGIC_VECTOR(575 DOWNTO 0); + mc_ADR : IN STD_LOGIC_VECTOR(143 DOWNTO 0); + mc_BA : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + mc_CKE : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + mc_CS_n : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + mc_ODT : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dBufAdr : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + rdDataAddr : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + wrDataAddr : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + winBuf : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + ddr4_act_n : OUT STD_LOGIC; + ddr4_adr : OUT STD_LOGIC_VECTOR(17 DOWNTO 0); + ddr4_ba : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + ddr4_bg : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + ddr4_par : OUT STD_LOGIC; + ddr4_cke : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + ddr4_odt : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + ddr4_cs_n : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + ddr4_ck_t : OUT STD_LOGIC; + ddr4_ck_c : OUT STD_LOGIC; + ddr4_reset_n : OUT STD_LOGIC; + ddr4_parity : OUT STD_LOGIC; + ddr4_dq : INOUT STD_LOGIC_VECTOR(71 DOWNTO 0); + ddr4_dqs_c : INOUT STD_LOGIC_VECTOR(17 DOWNTO 0); + ddr4_dqs_t : INOUT STD_LOGIC_VECTOR(17 DOWNTO 0); + mc_BG : IN STD_LOGIC_VECTOR(15 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : phy_ddr4 + PORT MAP ( + c0_init_calib_complete => c0_init_calib_complete, + dbg_clk => dbg_clk, + c0_sys_clk_p => c0_sys_clk_p, + c0_sys_clk_n => c0_sys_clk_n, + dbg_bus => dbg_bus, + c0_ddr4_parity => c0_ddr4_parity, + c0_ddr4_ui_clk => c0_ddr4_ui_clk, + c0_ddr4_ui_clk_sync_rst => c0_ddr4_ui_clk_sync_rst, + addn_ui_clkout1 => addn_ui_clkout1, + sys_rst => sys_rst, + rdDataEn => rdDataEn, + rdDataEnd => rdDataEnd, + per_rd_done => per_rd_done, + rmw_rd_done => rmw_rd_done, + wrDataEn => wrDataEn, + mc_ACT_n => mc_ACT_n, + mcCasSlot => mcCasSlot, + mcCasSlot2 => mcCasSlot2, + mcRdCAS => mcRdCAS, + mcWrCAS => mcWrCAS, + winInjTxn => winInjTxn, + winRmw => winRmw, + gt_data_ready => gt_data_ready, + winRank => winRank, + tCWL => tCWL, + wrData => wrData, + rdData => rdData, + mc_ADR => mc_ADR, + mc_BA => mc_BA, + mc_CKE => mc_CKE, + mc_CS_n => mc_CS_n, + mc_ODT => mc_ODT, + dBufAdr => dBufAdr, + rdDataAddr => rdDataAddr, + wrDataAddr => wrDataAddr, + winBuf => winBuf, + ddr4_act_n => ddr4_act_n, + ddr4_adr => ddr4_adr, + ddr4_ba => ddr4_ba, + ddr4_bg => ddr4_bg, + ddr4_par => ddr4_par, + ddr4_cke => ddr4_cke, + ddr4_odt => ddr4_odt, + ddr4_cs_n => ddr4_cs_n, + ddr4_ck_t => ddr4_ck_t, + ddr4_ck_c => ddr4_ck_c, + ddr4_reset_n => ddr4_reset_n, + ddr4_parity => ddr4_parity, + ddr4_dq => ddr4_dq, + ddr4_dqs_c => ddr4_dqs_c, + ddr4_dqs_t => ddr4_dqs_t, + mc_BG => mc_BG + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file phy_ddr4.vhd when simulating +-- the core, phy_ddr4. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U200/U200.ip_user_files/ip/phy_ddr4/phy_ddr4_stub.v b/projects/U200/U200.ip_user_files/ip/phy_ddr4/phy_ddr4_stub.v new file mode 100644 index 0000000..2543dd3 --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/phy_ddr4/phy_ddr4_stub.v @@ -0,0 +1,76 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Tue Mar 8 14:28:29 2022 +// Host : machine running 64-bit Ubuntu 20.04.4 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/phy_ddr4_stub.v +// Design : phy_ddr4 +// Purpose : Stub declaration of top-level module interface +// Device : xcu200-fsgd2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "ddr4_v2_2_10,Vivado 2020.2" *) +module phy_ddr4(sys_rst, c0_sys_clk_p, c0_sys_clk_n, + c0_ddr4_ui_clk, c0_ddr4_ui_clk_sync_rst, dbg_clk, c0_ddr4_act_n, c0_ddr4_adr, c0_ddr4_ba, + c0_ddr4_bg, c0_ddr4_cke, c0_ddr4_odt, c0_ddr4_cs_n, c0_ddr4_ck_t, c0_ddr4_ck_c, + c0_ddr4_reset_n, c0_ddr4_parity, c0_ddr4_dq, c0_ddr4_dqs_c, c0_ddr4_dqs_t, + c0_init_calib_complete, addn_ui_clkout1, dBufAdr, wrData, rdData, rdDataAddr, rdDataEn, + rdDataEnd, per_rd_done, rmw_rd_done, wrDataAddr, wrDataEn, mc_ACT_n, mc_ADR, mc_BA, mc_BG, mc_CKE, + mc_CS_n, mc_ODT, mcCasSlot, mcCasSlot2, mcRdCAS, mcWrCAS, winInjTxn, winRmw, gt_data_ready, winBuf, + winRank, tCWL, dbg_bus) +/* synthesis syn_black_box black_box_pad_pin="sys_rst,c0_sys_clk_p,c0_sys_clk_n,c0_ddr4_ui_clk,c0_ddr4_ui_clk_sync_rst,dbg_clk,c0_ddr4_act_n,c0_ddr4_adr[17:0],c0_ddr4_ba[1:0],c0_ddr4_bg[1:0],c0_ddr4_cke[0:0],c0_ddr4_odt[0:0],c0_ddr4_cs_n[0:0],c0_ddr4_ck_t[0:0],c0_ddr4_ck_c[0:0],c0_ddr4_reset_n,c0_ddr4_parity,c0_ddr4_dq[71:0],c0_ddr4_dqs_c[17:0],c0_ddr4_dqs_t[17:0],c0_init_calib_complete,addn_ui_clkout1,dBufAdr[4:0],wrData[575:0],rdData[575:0],rdDataAddr[4:0],rdDataEn[0:0],rdDataEnd[0:0],per_rd_done[0:0],rmw_rd_done[0:0],wrDataAddr[4:0],wrDataEn[0:0],mc_ACT_n[7:0],mc_ADR[143:0],mc_BA[15:0],mc_BG[15:0],mc_CKE[7:0],mc_CS_n[7:0],mc_ODT[7:0],mcCasSlot[1:0],mcCasSlot2[0:0],mcRdCAS[0:0],mcWrCAS[0:0],winInjTxn[0:0],winRmw[0:0],gt_data_ready,winBuf[4:0],winRank[1:0],tCWL[5:0],dbg_bus[511:0]" */; + input sys_rst; + input c0_sys_clk_p; + input c0_sys_clk_n; + output c0_ddr4_ui_clk; + output c0_ddr4_ui_clk_sync_rst; + output dbg_clk; + output c0_ddr4_act_n; + output [17:0]c0_ddr4_adr; + output [1:0]c0_ddr4_ba; + output [1:0]c0_ddr4_bg; + output [0:0]c0_ddr4_cke; + output [0:0]c0_ddr4_odt; + output [0:0]c0_ddr4_cs_n; + output [0:0]c0_ddr4_ck_t; + output [0:0]c0_ddr4_ck_c; + output c0_ddr4_reset_n; + output c0_ddr4_parity; + inout [71:0]c0_ddr4_dq; + inout [17:0]c0_ddr4_dqs_c; + inout [17:0]c0_ddr4_dqs_t; + output c0_init_calib_complete; + output addn_ui_clkout1; + input [4:0]dBufAdr; + input [575:0]wrData; + output [575:0]rdData; + output [4:0]rdDataAddr; + output [0:0]rdDataEn; + output [0:0]rdDataEnd; + output [0:0]per_rd_done; + output [0:0]rmw_rd_done; + output [4:0]wrDataAddr; + output [0:0]wrDataEn; + input [7:0]mc_ACT_n; + input [143:0]mc_ADR; + input [15:0]mc_BA; + input [15:0]mc_BG; + input [7:0]mc_CKE; + input [7:0]mc_CS_n; + input [7:0]mc_ODT; + input [1:0]mcCasSlot; + input [0:0]mcCasSlot2; + input [0:0]mcRdCAS; + input [0:0]mcWrCAS; + input [0:0]winInjTxn; + input [0:0]winRmw; + input gt_data_ready; + input [4:0]winBuf; + input [1:0]winRank; + output [5:0]tCWL; + output [511:0]dbg_bus; +endmodule diff --git a/projects/U200/U200.ip_user_files/ip/phy_ddr4/phy_ddr4_stub.vhdl b/projects/U200/U200.ip_user_files/ip/phy_ddr4/phy_ddr4_stub.vhdl new file mode 100644 index 0000000..8cec2be --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/phy_ddr4/phy_ddr4_stub.vhdl @@ -0,0 +1,79 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Tue Mar 8 14:28:29 2022 +-- Host : machine running 64-bit Ubuntu 20.04.4 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/phy_ddr4_stub.vhdl +-- Design : phy_ddr4 +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu200-fsgd2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity phy_ddr4 is + Port ( + sys_rst : in STD_LOGIC; + c0_sys_clk_p : in STD_LOGIC; + c0_sys_clk_n : in STD_LOGIC; + c0_ddr4_ui_clk : out STD_LOGIC; + c0_ddr4_ui_clk_sync_rst : out STD_LOGIC; + dbg_clk : out STD_LOGIC; + c0_ddr4_act_n : out STD_LOGIC; + c0_ddr4_adr : out STD_LOGIC_VECTOR ( 17 downto 0 ); + c0_ddr4_ba : out STD_LOGIC_VECTOR ( 1 downto 0 ); + c0_ddr4_bg : out STD_LOGIC_VECTOR ( 1 downto 0 ); + c0_ddr4_cke : out STD_LOGIC_VECTOR ( 0 to 0 ); + c0_ddr4_odt : out STD_LOGIC_VECTOR ( 0 to 0 ); + c0_ddr4_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 ); + c0_ddr4_ck_t : out STD_LOGIC_VECTOR ( 0 to 0 ); + c0_ddr4_ck_c : out STD_LOGIC_VECTOR ( 0 to 0 ); + c0_ddr4_reset_n : out STD_LOGIC; + c0_ddr4_parity : out STD_LOGIC; + c0_ddr4_dq : inout STD_LOGIC_VECTOR ( 71 downto 0 ); + c0_ddr4_dqs_c : inout STD_LOGIC_VECTOR ( 17 downto 0 ); + c0_ddr4_dqs_t : inout STD_LOGIC_VECTOR ( 17 downto 0 ); + c0_init_calib_complete : out STD_LOGIC; + addn_ui_clkout1 : out STD_LOGIC; + dBufAdr : in STD_LOGIC_VECTOR ( 4 downto 0 ); + wrData : in STD_LOGIC_VECTOR ( 575 downto 0 ); + rdData : out STD_LOGIC_VECTOR ( 575 downto 0 ); + rdDataAddr : out STD_LOGIC_VECTOR ( 4 downto 0 ); + rdDataEn : out STD_LOGIC_VECTOR ( 0 to 0 ); + rdDataEnd : out STD_LOGIC_VECTOR ( 0 to 0 ); + per_rd_done : out STD_LOGIC_VECTOR ( 0 to 0 ); + rmw_rd_done : out STD_LOGIC_VECTOR ( 0 to 0 ); + wrDataAddr : out STD_LOGIC_VECTOR ( 4 downto 0 ); + wrDataEn : out STD_LOGIC_VECTOR ( 0 to 0 ); + mc_ACT_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); + mc_ADR : in STD_LOGIC_VECTOR ( 143 downto 0 ); + mc_BA : in STD_LOGIC_VECTOR ( 15 downto 0 ); + mc_BG : in STD_LOGIC_VECTOR ( 15 downto 0 ); + mc_CKE : in STD_LOGIC_VECTOR ( 7 downto 0 ); + mc_CS_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); + mc_ODT : in STD_LOGIC_VECTOR ( 7 downto 0 ); + mcCasSlot : in STD_LOGIC_VECTOR ( 1 downto 0 ); + mcCasSlot2 : in STD_LOGIC_VECTOR ( 0 to 0 ); + mcRdCAS : in STD_LOGIC_VECTOR ( 0 to 0 ); + mcWrCAS : in STD_LOGIC_VECTOR ( 0 to 0 ); + winInjTxn : in STD_LOGIC_VECTOR ( 0 to 0 ); + winRmw : in STD_LOGIC_VECTOR ( 0 to 0 ); + gt_data_ready : in STD_LOGIC; + winBuf : in STD_LOGIC_VECTOR ( 4 downto 0 ); + winRank : in STD_LOGIC_VECTOR ( 1 downto 0 ); + tCWL : out STD_LOGIC_VECTOR ( 5 downto 0 ); + dbg_bus : out STD_LOGIC_VECTOR ( 511 downto 0 ) + ); + +end phy_ddr4; + +architecture stub of phy_ddr4 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "sys_rst,c0_sys_clk_p,c0_sys_clk_n,c0_ddr4_ui_clk,c0_ddr4_ui_clk_sync_rst,dbg_clk,c0_ddr4_act_n,c0_ddr4_adr[17:0],c0_ddr4_ba[1:0],c0_ddr4_bg[1:0],c0_ddr4_cke[0:0],c0_ddr4_odt[0:0],c0_ddr4_cs_n[0:0],c0_ddr4_ck_t[0:0],c0_ddr4_ck_c[0:0],c0_ddr4_reset_n,c0_ddr4_parity,c0_ddr4_dq[71:0],c0_ddr4_dqs_c[17:0],c0_ddr4_dqs_t[17:0],c0_init_calib_complete,addn_ui_clkout1,dBufAdr[4:0],wrData[575:0],rdData[575:0],rdDataAddr[4:0],rdDataEn[0:0],rdDataEnd[0:0],per_rd_done[0:0],rmw_rd_done[0:0],wrDataAddr[4:0],wrDataEn[0:0],mc_ACT_n[7:0],mc_ADR[143:0],mc_BA[15:0],mc_BG[15:0],mc_CKE[7:0],mc_CS_n[7:0],mc_ODT[7:0],mcCasSlot[1:0],mcCasSlot2[0:0],mcRdCAS[0:0],mcWrCAS[0:0],winInjTxn[0:0],winRmw[0:0],gt_data_ready,winBuf[4:0],winRank[1:0],tCWL[5:0],dbg_bus[511:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "ddr4_v2_2_10,Vivado 2020.2"; +begin +end; diff --git a/projects/U200/U200.ip_user_files/ip/phy_ddr4_udimm/phy_ddr4_udimm.veo b/projects/U200/U200.ip_user_files/ip/phy_ddr4_udimm/phy_ddr4_udimm.veo new file mode 100755 index 0000000..6d449e1 --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/phy_ddr4_udimm/phy_ddr4_udimm.veo @@ -0,0 +1,115 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:ddr4:2.2 +// IP Revision: 10 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +phy_ddr4_udimm your_instance_name ( + .c0_init_calib_complete(c0_init_calib_complete), // output wire c0_init_calib_complete + .dbg_clk(dbg_clk), // output wire dbg_clk + .c0_sys_clk_p(c0_sys_clk_p), // input wire c0_sys_clk_p + .c0_sys_clk_n(c0_sys_clk_n), // input wire c0_sys_clk_n + .dbg_bus(dbg_bus), // output wire [511 : 0] dbg_bus + .c0_ddr4_ui_clk(c0_ddr4_ui_clk), // output wire c0_ddr4_ui_clk + .c0_ddr4_ui_clk_sync_rst(c0_ddr4_ui_clk_sync_rst), // output wire c0_ddr4_ui_clk_sync_rst + .sys_rst(sys_rst), // input wire sys_rst + .rdDataEn(rdDataEn), // output wire [0 : 0] rdDataEn + .rdDataEnd(rdDataEnd), // output wire [0 : 0] rdDataEnd + .per_rd_done(per_rd_done), // output wire [0 : 0] per_rd_done + .rmw_rd_done(rmw_rd_done), // output wire [0 : 0] rmw_rd_done + .wrDataEn(wrDataEn), // output wire [0 : 0] wrDataEn + .mc_ACT_n(mc_ACT_n), // input wire [7 : 0] mc_ACT_n + .mcCasSlot(mcCasSlot), // input wire [1 : 0] mcCasSlot + .mcCasSlot2(mcCasSlot2), // input wire [0 : 0] mcCasSlot2 + .mcRdCAS(mcRdCAS), // input wire [0 : 0] mcRdCAS + .mcWrCAS(mcWrCAS), // input wire [0 : 0] mcWrCAS + .winInjTxn(winInjTxn), // input wire [0 : 0] winInjTxn + .winRmw(winRmw), // input wire [0 : 0] winRmw + .gt_data_ready(gt_data_ready), // input wire gt_data_ready + .winRank(winRank), // input wire [1 : 0] winRank + .tCWL(tCWL), // output wire [5 : 0] tCWL + .wrData(wrData), // input wire [511 : 0] wrData + .wrDataMask(wrDataMask), // input wire [63 : 0] wrDataMask + .rdData(rdData), // output wire [511 : 0] rdData + .mc_ADR(mc_ADR), // input wire [135 : 0] mc_ADR + .mc_BA(mc_BA), // input wire [15 : 0] mc_BA + .mc_CKE(mc_CKE), // input wire [7 : 0] mc_CKE + .mc_CS_n(mc_CS_n), // input wire [7 : 0] mc_CS_n + .mc_ODT(mc_ODT), // input wire [7 : 0] mc_ODT + .dBufAdr(dBufAdr), // input wire [4 : 0] dBufAdr + .rdDataAddr(rdDataAddr), // output wire [4 : 0] rdDataAddr + .wrDataAddr(wrDataAddr), // output wire [4 : 0] wrDataAddr + .winBuf(winBuf), // input wire [4 : 0] winBuf + .ddr4_act_n(ddr4_act_n), // output wire ddr4_act_n + .ddr4_adr(ddr4_adr), // output wire [16 : 0] ddr4_adr + .ddr4_ba(ddr4_ba), // output wire [1 : 0] ddr4_ba + .ddr4_bg(ddr4_bg), // output wire [1 : 0] ddr4_bg + .ddr4_par(ddr4_par), // output wire ddr4_par + .ddr4_cke(ddr4_cke), // output wire [0 : 0] ddr4_cke + .ddr4_odt(ddr4_odt), // output wire [0 : 0] ddr4_odt + .ddr4_cs_n(ddr4_cs_n), // output wire [0 : 0] ddr4_cs_n + .ddr4_ck_t(ddr4_ck_t), // output wire ddr4_ck_t + .ddr4_ck_c(ddr4_ck_c), // output wire ddr4_ck_c + .ddr4_reset_n(ddr4_reset_n), // output wire ddr4_reset_n + .ddr4_dm_dbi_n(ddr4_dm_dbi_n), // inout wire [7 : 0] ddr4_dm_dbi_n + .ddr4_dq(ddr4_dq), // inout wire [63 : 0] ddr4_dq + .ddr4_dqs_c(ddr4_dqs_c), // inout wire [7 : 0] ddr4_dqs_c + .ddr4_dqs_t(ddr4_dqs_t), // inout wire [7 : 0] ddr4_dqs_t + .mc_BG(mc_BG) // input wire [15 : 0] mc_BG +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file phy_ddr4_udimm.v when simulating +// the core, phy_ddr4_udimm. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U200/U200.ip_user_files/ip/phy_ddr4_udimm/phy_ddr4_udimm.vho b/projects/U200/U200.ip_user_files/ip/phy_ddr4_udimm/phy_ddr4_udimm.vho new file mode 100755 index 0000000..6c9bb1d --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/phy_ddr4_udimm/phy_ddr4_udimm.vho @@ -0,0 +1,175 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:ddr4:2.2 +-- IP Revision: 10 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT phy_ddr4_udimm + PORT ( + c0_init_calib_complete : OUT STD_LOGIC; + dbg_clk : OUT STD_LOGIC; + c0_sys_clk_p : IN STD_LOGIC; + c0_sys_clk_n : IN STD_LOGIC; + dbg_bus : OUT STD_LOGIC_VECTOR(511 DOWNTO 0); + c0_ddr4_ui_clk : OUT STD_LOGIC; + c0_ddr4_ui_clk_sync_rst : OUT STD_LOGIC; + sys_rst : IN STD_LOGIC; + rdDataEn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + rdDataEnd : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + per_rd_done : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + rmw_rd_done : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + wrDataEn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + mc_ACT_n : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + mcCasSlot : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + mcCasSlot2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + mcRdCAS : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + mcWrCAS : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + winInjTxn : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + winRmw : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_data_ready : IN STD_LOGIC; + winRank : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + tCWL : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + wrData : IN STD_LOGIC_VECTOR(511 DOWNTO 0); + wrDataMask : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + rdData : OUT STD_LOGIC_VECTOR(511 DOWNTO 0); + mc_ADR : IN STD_LOGIC_VECTOR(135 DOWNTO 0); + mc_BA : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + mc_CKE : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + mc_CS_n : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + mc_ODT : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dBufAdr : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + rdDataAddr : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + wrDataAddr : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + winBuf : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + ddr4_act_n : OUT STD_LOGIC; + ddr4_adr : OUT STD_LOGIC_VECTOR(16 DOWNTO 0); + ddr4_ba : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + ddr4_bg : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + ddr4_par : OUT STD_LOGIC; + ddr4_cke : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + ddr4_odt : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + ddr4_cs_n : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + ddr4_ck_t : OUT STD_LOGIC; + ddr4_ck_c : OUT STD_LOGIC; + ddr4_reset_n : OUT STD_LOGIC; + ddr4_dm_dbi_n : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); + ddr4_dq : INOUT STD_LOGIC_VECTOR(63 DOWNTO 0); + ddr4_dqs_c : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); + ddr4_dqs_t : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); + mc_BG : IN STD_LOGIC_VECTOR(15 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : phy_ddr4_udimm + PORT MAP ( + c0_init_calib_complete => c0_init_calib_complete, + dbg_clk => dbg_clk, + c0_sys_clk_p => c0_sys_clk_p, + c0_sys_clk_n => c0_sys_clk_n, + dbg_bus => dbg_bus, + c0_ddr4_ui_clk => c0_ddr4_ui_clk, + c0_ddr4_ui_clk_sync_rst => c0_ddr4_ui_clk_sync_rst, + sys_rst => sys_rst, + rdDataEn => rdDataEn, + rdDataEnd => rdDataEnd, + per_rd_done => per_rd_done, + rmw_rd_done => rmw_rd_done, + wrDataEn => wrDataEn, + mc_ACT_n => mc_ACT_n, + mcCasSlot => mcCasSlot, + mcCasSlot2 => mcCasSlot2, + mcRdCAS => mcRdCAS, + mcWrCAS => mcWrCAS, + winInjTxn => winInjTxn, + winRmw => winRmw, + gt_data_ready => gt_data_ready, + winRank => winRank, + tCWL => tCWL, + wrData => wrData, + wrDataMask => wrDataMask, + rdData => rdData, + mc_ADR => mc_ADR, + mc_BA => mc_BA, + mc_CKE => mc_CKE, + mc_CS_n => mc_CS_n, + mc_ODT => mc_ODT, + dBufAdr => dBufAdr, + rdDataAddr => rdDataAddr, + wrDataAddr => wrDataAddr, + winBuf => winBuf, + ddr4_act_n => ddr4_act_n, + ddr4_adr => ddr4_adr, + ddr4_ba => ddr4_ba, + ddr4_bg => ddr4_bg, + ddr4_par => ddr4_par, + ddr4_cke => ddr4_cke, + ddr4_odt => ddr4_odt, + ddr4_cs_n => ddr4_cs_n, + ddr4_ck_t => ddr4_ck_t, + ddr4_ck_c => ddr4_ck_c, + ddr4_reset_n => ddr4_reset_n, + ddr4_dm_dbi_n => ddr4_dm_dbi_n, + ddr4_dq => ddr4_dq, + ddr4_dqs_c => ddr4_dqs_c, + ddr4_dqs_t => ddr4_dqs_t, + mc_BG => mc_BG + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file phy_ddr4_udimm.vhd when simulating +-- the core, phy_ddr4_udimm. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U200/U200.ip_user_files/ip/phy_ddr4_udimm/phy_ddr4_udimm_stub.v b/projects/U200/U200.ip_user_files/ip/phy_ddr4_udimm/phy_ddr4_udimm_stub.v new file mode 100644 index 0000000..d128321 --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/phy_ddr4_udimm/phy_ddr4_udimm_stub.v @@ -0,0 +1,76 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Tue Mar 8 15:10:27 2022 +// Host : machine running 64-bit Ubuntu 20.04.4 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/phy_ddr4_udimm_stub.v +// Design : phy_ddr4_udimm +// Purpose : Stub declaration of top-level module interface +// Device : xcu200-fsgd2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "ddr4_v2_2_10,Vivado 2020.2" *) +module phy_ddr4_udimm(sys_rst, c0_sys_clk_p, c0_sys_clk_n, + c0_ddr4_ui_clk, c0_ddr4_ui_clk_sync_rst, dbg_clk, c0_ddr4_act_n, c0_ddr4_adr, c0_ddr4_ba, + c0_ddr4_bg, c0_ddr4_cke, c0_ddr4_odt, c0_ddr4_cs_n, c0_ddr4_ck_t, c0_ddr4_ck_c, + c0_ddr4_reset_n, c0_ddr4_dm_dbi_n, c0_ddr4_dq, c0_ddr4_dqs_c, c0_ddr4_dqs_t, + c0_init_calib_complete, dBufAdr, wrData, wrDataMask, rdData, rdDataAddr, rdDataEn, rdDataEnd, + per_rd_done, rmw_rd_done, wrDataAddr, wrDataEn, mc_ACT_n, mc_ADR, mc_BA, mc_BG, mc_CKE, mc_CS_n, + mc_ODT, mcCasSlot, mcCasSlot2, mcRdCAS, mcWrCAS, winInjTxn, winRmw, gt_data_ready, winBuf, winRank, + tCWL, dbg_bus) +/* synthesis syn_black_box black_box_pad_pin="sys_rst,c0_sys_clk_p,c0_sys_clk_n,c0_ddr4_ui_clk,c0_ddr4_ui_clk_sync_rst,dbg_clk,c0_ddr4_act_n,c0_ddr4_adr[16:0],c0_ddr4_ba[1:0],c0_ddr4_bg[1:0],c0_ddr4_cke[0:0],c0_ddr4_odt[0:0],c0_ddr4_cs_n[0:0],c0_ddr4_ck_t[0:0],c0_ddr4_ck_c[0:0],c0_ddr4_reset_n,c0_ddr4_dm_dbi_n[7:0],c0_ddr4_dq[63:0],c0_ddr4_dqs_c[7:0],c0_ddr4_dqs_t[7:0],c0_init_calib_complete,dBufAdr[4:0],wrData[511:0],wrDataMask[63:0],rdData[511:0],rdDataAddr[4:0],rdDataEn[0:0],rdDataEnd[0:0],per_rd_done[0:0],rmw_rd_done[0:0],wrDataAddr[4:0],wrDataEn[0:0],mc_ACT_n[7:0],mc_ADR[135:0],mc_BA[15:0],mc_BG[15:0],mc_CKE[7:0],mc_CS_n[7:0],mc_ODT[7:0],mcCasSlot[1:0],mcCasSlot2[0:0],mcRdCAS[0:0],mcWrCAS[0:0],winInjTxn[0:0],winRmw[0:0],gt_data_ready,winBuf[4:0],winRank[1:0],tCWL[5:0],dbg_bus[511:0]" */; + input sys_rst; + input c0_sys_clk_p; + input c0_sys_clk_n; + output c0_ddr4_ui_clk; + output c0_ddr4_ui_clk_sync_rst; + output dbg_clk; + output c0_ddr4_act_n; + output [16:0]c0_ddr4_adr; + output [1:0]c0_ddr4_ba; + output [1:0]c0_ddr4_bg; + output [0:0]c0_ddr4_cke; + output [0:0]c0_ddr4_odt; + output [0:0]c0_ddr4_cs_n; + output [0:0]c0_ddr4_ck_t; + output [0:0]c0_ddr4_ck_c; + output c0_ddr4_reset_n; + inout [7:0]c0_ddr4_dm_dbi_n; + inout [63:0]c0_ddr4_dq; + inout [7:0]c0_ddr4_dqs_c; + inout [7:0]c0_ddr4_dqs_t; + output c0_init_calib_complete; + input [4:0]dBufAdr; + input [511:0]wrData; + input [63:0]wrDataMask; + output [511:0]rdData; + output [4:0]rdDataAddr; + output [0:0]rdDataEn; + output [0:0]rdDataEnd; + output [0:0]per_rd_done; + output [0:0]rmw_rd_done; + output [4:0]wrDataAddr; + output [0:0]wrDataEn; + input [7:0]mc_ACT_n; + input [135:0]mc_ADR; + input [15:0]mc_BA; + input [15:0]mc_BG; + input [7:0]mc_CKE; + input [7:0]mc_CS_n; + input [7:0]mc_ODT; + input [1:0]mcCasSlot; + input [0:0]mcCasSlot2; + input [0:0]mcRdCAS; + input [0:0]mcWrCAS; + input [0:0]winInjTxn; + input [0:0]winRmw; + input gt_data_ready; + input [4:0]winBuf; + input [1:0]winRank; + output [5:0]tCWL; + output [511:0]dbg_bus; +endmodule diff --git a/projects/U200/U200.ip_user_files/ip/phy_ddr4_udimm/phy_ddr4_udimm_stub.vhdl b/projects/U200/U200.ip_user_files/ip/phy_ddr4_udimm/phy_ddr4_udimm_stub.vhdl new file mode 100644 index 0000000..e598825 --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/phy_ddr4_udimm/phy_ddr4_udimm_stub.vhdl @@ -0,0 +1,79 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Tue Mar 8 15:10:28 2022 +-- Host : machine running 64-bit Ubuntu 20.04.4 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/phy_ddr4_udimm_stub.vhdl +-- Design : phy_ddr4_udimm +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu200-fsgd2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity phy_ddr4_udimm is + Port ( + sys_rst : in STD_LOGIC; + c0_sys_clk_p : in STD_LOGIC; + c0_sys_clk_n : in STD_LOGIC; + c0_ddr4_ui_clk : out STD_LOGIC; + c0_ddr4_ui_clk_sync_rst : out STD_LOGIC; + dbg_clk : out STD_LOGIC; + c0_ddr4_act_n : out STD_LOGIC; + c0_ddr4_adr : out STD_LOGIC_VECTOR ( 16 downto 0 ); + c0_ddr4_ba : out STD_LOGIC_VECTOR ( 1 downto 0 ); + c0_ddr4_bg : out STD_LOGIC_VECTOR ( 1 downto 0 ); + c0_ddr4_cke : out STD_LOGIC_VECTOR ( 0 to 0 ); + c0_ddr4_odt : out STD_LOGIC_VECTOR ( 0 to 0 ); + c0_ddr4_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 ); + c0_ddr4_ck_t : out STD_LOGIC_VECTOR ( 0 to 0 ); + c0_ddr4_ck_c : out STD_LOGIC_VECTOR ( 0 to 0 ); + c0_ddr4_reset_n : out STD_LOGIC; + c0_ddr4_dm_dbi_n : inout STD_LOGIC_VECTOR ( 7 downto 0 ); + c0_ddr4_dq : inout STD_LOGIC_VECTOR ( 63 downto 0 ); + c0_ddr4_dqs_c : inout STD_LOGIC_VECTOR ( 7 downto 0 ); + c0_ddr4_dqs_t : inout STD_LOGIC_VECTOR ( 7 downto 0 ); + c0_init_calib_complete : out STD_LOGIC; + dBufAdr : in STD_LOGIC_VECTOR ( 4 downto 0 ); + wrData : in STD_LOGIC_VECTOR ( 511 downto 0 ); + wrDataMask : in STD_LOGIC_VECTOR ( 63 downto 0 ); + rdData : out STD_LOGIC_VECTOR ( 511 downto 0 ); + rdDataAddr : out STD_LOGIC_VECTOR ( 4 downto 0 ); + rdDataEn : out STD_LOGIC_VECTOR ( 0 to 0 ); + rdDataEnd : out STD_LOGIC_VECTOR ( 0 to 0 ); + per_rd_done : out STD_LOGIC_VECTOR ( 0 to 0 ); + rmw_rd_done : out STD_LOGIC_VECTOR ( 0 to 0 ); + wrDataAddr : out STD_LOGIC_VECTOR ( 4 downto 0 ); + wrDataEn : out STD_LOGIC_VECTOR ( 0 to 0 ); + mc_ACT_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); + mc_ADR : in STD_LOGIC_VECTOR ( 135 downto 0 ); + mc_BA : in STD_LOGIC_VECTOR ( 15 downto 0 ); + mc_BG : in STD_LOGIC_VECTOR ( 15 downto 0 ); + mc_CKE : in STD_LOGIC_VECTOR ( 7 downto 0 ); + mc_CS_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); + mc_ODT : in STD_LOGIC_VECTOR ( 7 downto 0 ); + mcCasSlot : in STD_LOGIC_VECTOR ( 1 downto 0 ); + mcCasSlot2 : in STD_LOGIC_VECTOR ( 0 to 0 ); + mcRdCAS : in STD_LOGIC_VECTOR ( 0 to 0 ); + mcWrCAS : in STD_LOGIC_VECTOR ( 0 to 0 ); + winInjTxn : in STD_LOGIC_VECTOR ( 0 to 0 ); + winRmw : in STD_LOGIC_VECTOR ( 0 to 0 ); + gt_data_ready : in STD_LOGIC; + winBuf : in STD_LOGIC_VECTOR ( 4 downto 0 ); + winRank : in STD_LOGIC_VECTOR ( 1 downto 0 ); + tCWL : out STD_LOGIC_VECTOR ( 5 downto 0 ); + dbg_bus : out STD_LOGIC_VECTOR ( 511 downto 0 ) + ); + +end phy_ddr4_udimm; + +architecture stub of phy_ddr4_udimm is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "sys_rst,c0_sys_clk_p,c0_sys_clk_n,c0_ddr4_ui_clk,c0_ddr4_ui_clk_sync_rst,dbg_clk,c0_ddr4_act_n,c0_ddr4_adr[16:0],c0_ddr4_ba[1:0],c0_ddr4_bg[1:0],c0_ddr4_cke[0:0],c0_ddr4_odt[0:0],c0_ddr4_cs_n[0:0],c0_ddr4_ck_t[0:0],c0_ddr4_ck_c[0:0],c0_ddr4_reset_n,c0_ddr4_dm_dbi_n[7:0],c0_ddr4_dq[63:0],c0_ddr4_dqs_c[7:0],c0_ddr4_dqs_t[7:0],c0_init_calib_complete,dBufAdr[4:0],wrData[511:0],wrDataMask[63:0],rdData[511:0],rdDataAddr[4:0],rdDataEn[0:0],rdDataEnd[0:0],per_rd_done[0:0],rmw_rd_done[0:0],wrDataAddr[4:0],wrDataEn[0:0],mc_ACT_n[7:0],mc_ADR[135:0],mc_BA[15:0],mc_BG[15:0],mc_CKE[7:0],mc_CS_n[7:0],mc_ODT[7:0],mcCasSlot[1:0],mcCasSlot2[0:0],mcRdCAS[0:0],mcWrCAS[0:0],winInjTxn[0:0],winRmw[0:0],gt_data_ready,winBuf[4:0],winRank[1:0],tCWL[5:0],dbg_bus[511:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "ddr4_v2_2_10,Vivado 2020.2"; +begin +end; diff --git a/projects/U200/U200.ip_user_files/ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual.veo b/projects/U200/U200.ip_user_files/ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual.veo new file mode 100755 index 0000000..4848a52 --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual.veo @@ -0,0 +1,117 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:ddr4:2.2 +// IP Revision: 10 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +phy_rdimm_x8_dual your_instance_name ( + .c0_init_calib_complete(c0_init_calib_complete), // output wire c0_init_calib_complete + .dbg_clk(dbg_clk), // output wire dbg_clk + .c0_sys_clk_p(c0_sys_clk_p), // input wire c0_sys_clk_p + .c0_sys_clk_n(c0_sys_clk_n), // input wire c0_sys_clk_n + .dbg_bus(dbg_bus), // output wire [511 : 0] dbg_bus + .c0_ddr4_parity(c0_ddr4_parity), // output wire c0_ddr4_parity + .c0_ddr4_ui_clk(c0_ddr4_ui_clk), // output wire c0_ddr4_ui_clk + .c0_ddr4_ui_clk_sync_rst(c0_ddr4_ui_clk_sync_rst), // output wire c0_ddr4_ui_clk_sync_rst + .sys_rst(sys_rst), // input wire sys_rst + .rdDataEn(rdDataEn), // output wire [0 : 0] rdDataEn + .rdDataEnd(rdDataEnd), // output wire [0 : 0] rdDataEnd + .per_rd_done(per_rd_done), // output wire [0 : 0] per_rd_done + .rmw_rd_done(rmw_rd_done), // output wire [0 : 0] rmw_rd_done + .wrDataEn(wrDataEn), // output wire [0 : 0] wrDataEn + .mc_ACT_n(mc_ACT_n), // input wire [7 : 0] mc_ACT_n + .mcCasSlot(mcCasSlot), // input wire [1 : 0] mcCasSlot + .mcCasSlot2(mcCasSlot2), // input wire [0 : 0] mcCasSlot2 + .mcRdCAS(mcRdCAS), // input wire [0 : 0] mcRdCAS + .mcWrCAS(mcWrCAS), // input wire [0 : 0] mcWrCAS + .winInjTxn(winInjTxn), // input wire [0 : 0] winInjTxn + .winRmw(winRmw), // input wire [0 : 0] winRmw + .gt_data_ready(gt_data_ready), // input wire gt_data_ready + .winRank(winRank), // input wire [1 : 0] winRank + .tCWL(tCWL), // output wire [5 : 0] tCWL + .wrData(wrData), // input wire [575 : 0] wrData + .wrDataMask(wrDataMask), // input wire [71 : 0] wrDataMask + .rdData(rdData), // output wire [575 : 0] rdData + .mc_ADR(mc_ADR), // input wire [135 : 0] mc_ADR + .mc_BA(mc_BA), // input wire [15 : 0] mc_BA + .mc_CKE(mc_CKE), // input wire [7 : 0] mc_CKE + .mc_CS_n(mc_CS_n), // input wire [7 : 0] mc_CS_n + .mc_ODT(mc_ODT), // input wire [7 : 0] mc_ODT + .dBufAdr(dBufAdr), // input wire [4 : 0] dBufAdr + .rdDataAddr(rdDataAddr), // output wire [4 : 0] rdDataAddr + .wrDataAddr(wrDataAddr), // output wire [4 : 0] wrDataAddr + .winBuf(winBuf), // input wire [4 : 0] winBuf + .ddr4_act_n(ddr4_act_n), // output wire ddr4_act_n + .ddr4_adr(ddr4_adr), // output wire [16 : 0] ddr4_adr + .ddr4_ba(ddr4_ba), // output wire [1 : 0] ddr4_ba + .ddr4_bg(ddr4_bg), // output wire [1 : 0] ddr4_bg + .ddr4_par(ddr4_par), // output wire ddr4_par + .ddr4_cke(ddr4_cke), // output wire [0 : 0] ddr4_cke + .ddr4_odt(ddr4_odt), // output wire [0 : 0] ddr4_odt + .ddr4_cs_n(ddr4_cs_n), // output wire [0 : 0] ddr4_cs_n + .ddr4_ck_t(ddr4_ck_t), // output wire ddr4_ck_t + .ddr4_ck_c(ddr4_ck_c), // output wire ddr4_ck_c + .ddr4_reset_n(ddr4_reset_n), // output wire ddr4_reset_n + .ddr4_parity(ddr4_parity), // output wire ddr4_parity + .ddr4_dm_dbi_n(ddr4_dm_dbi_n), // inout wire [8 : 0] ddr4_dm_dbi_n + .ddr4_dq(ddr4_dq), // inout wire [71 : 0] ddr4_dq + .ddr4_dqs_c(ddr4_dqs_c), // inout wire [8 : 0] ddr4_dqs_c + .ddr4_dqs_t(ddr4_dqs_t), // inout wire [8 : 0] ddr4_dqs_t + .mc_BG(mc_BG) // input wire [15 : 0] mc_BG +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file phy_rdimm_x8_dual.v when simulating +// the core, phy_rdimm_x8_dual. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U200/U200.ip_user_files/ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual.vho b/projects/U200/U200.ip_user_files/ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual.vho new file mode 100755 index 0000000..e5803d2 --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual.vho @@ -0,0 +1,179 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:ddr4:2.2 +-- IP Revision: 10 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT phy_rdimm_x8_dual + PORT ( + c0_init_calib_complete : OUT STD_LOGIC; + dbg_clk : OUT STD_LOGIC; + c0_sys_clk_p : IN STD_LOGIC; + c0_sys_clk_n : IN STD_LOGIC; + dbg_bus : OUT STD_LOGIC_VECTOR(511 DOWNTO 0); + c0_ddr4_parity : OUT STD_LOGIC; + c0_ddr4_ui_clk : OUT STD_LOGIC; + c0_ddr4_ui_clk_sync_rst : OUT STD_LOGIC; + sys_rst : IN STD_LOGIC; + rdDataEn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + rdDataEnd : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + per_rd_done : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + rmw_rd_done : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + wrDataEn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + mc_ACT_n : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + mcCasSlot : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + mcCasSlot2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + mcRdCAS : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + mcWrCAS : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + winInjTxn : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + winRmw : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + gt_data_ready : IN STD_LOGIC; + winRank : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + tCWL : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + wrData : IN STD_LOGIC_VECTOR(575 DOWNTO 0); + wrDataMask : IN STD_LOGIC_VECTOR(71 DOWNTO 0); + rdData : OUT STD_LOGIC_VECTOR(575 DOWNTO 0); + mc_ADR : IN STD_LOGIC_VECTOR(135 DOWNTO 0); + mc_BA : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + mc_CKE : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + mc_CS_n : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + mc_ODT : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dBufAdr : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + rdDataAddr : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + wrDataAddr : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + winBuf : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + ddr4_act_n : OUT STD_LOGIC; + ddr4_adr : OUT STD_LOGIC_VECTOR(16 DOWNTO 0); + ddr4_ba : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + ddr4_bg : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + ddr4_par : OUT STD_LOGIC; + ddr4_cke : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + ddr4_odt : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + ddr4_cs_n : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + ddr4_ck_t : OUT STD_LOGIC; + ddr4_ck_c : OUT STD_LOGIC; + ddr4_reset_n : OUT STD_LOGIC; + ddr4_parity : OUT STD_LOGIC; + ddr4_dm_dbi_n : INOUT STD_LOGIC_VECTOR(8 DOWNTO 0); + ddr4_dq : INOUT STD_LOGIC_VECTOR(71 DOWNTO 0); + ddr4_dqs_c : INOUT STD_LOGIC_VECTOR(8 DOWNTO 0); + ddr4_dqs_t : INOUT STD_LOGIC_VECTOR(8 DOWNTO 0); + mc_BG : IN STD_LOGIC_VECTOR(15 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : phy_rdimm_x8_dual + PORT MAP ( + c0_init_calib_complete => c0_init_calib_complete, + dbg_clk => dbg_clk, + c0_sys_clk_p => c0_sys_clk_p, + c0_sys_clk_n => c0_sys_clk_n, + dbg_bus => dbg_bus, + c0_ddr4_parity => c0_ddr4_parity, + c0_ddr4_ui_clk => c0_ddr4_ui_clk, + c0_ddr4_ui_clk_sync_rst => c0_ddr4_ui_clk_sync_rst, + sys_rst => sys_rst, + rdDataEn => rdDataEn, + rdDataEnd => rdDataEnd, + per_rd_done => per_rd_done, + rmw_rd_done => rmw_rd_done, + wrDataEn => wrDataEn, + mc_ACT_n => mc_ACT_n, + mcCasSlot => mcCasSlot, + mcCasSlot2 => mcCasSlot2, + mcRdCAS => mcRdCAS, + mcWrCAS => mcWrCAS, + winInjTxn => winInjTxn, + winRmw => winRmw, + gt_data_ready => gt_data_ready, + winRank => winRank, + tCWL => tCWL, + wrData => wrData, + wrDataMask => wrDataMask, + rdData => rdData, + mc_ADR => mc_ADR, + mc_BA => mc_BA, + mc_CKE => mc_CKE, + mc_CS_n => mc_CS_n, + mc_ODT => mc_ODT, + dBufAdr => dBufAdr, + rdDataAddr => rdDataAddr, + wrDataAddr => wrDataAddr, + winBuf => winBuf, + ddr4_act_n => ddr4_act_n, + ddr4_adr => ddr4_adr, + ddr4_ba => ddr4_ba, + ddr4_bg => ddr4_bg, + ddr4_par => ddr4_par, + ddr4_cke => ddr4_cke, + ddr4_odt => ddr4_odt, + ddr4_cs_n => ddr4_cs_n, + ddr4_ck_t => ddr4_ck_t, + ddr4_ck_c => ddr4_ck_c, + ddr4_reset_n => ddr4_reset_n, + ddr4_parity => ddr4_parity, + ddr4_dm_dbi_n => ddr4_dm_dbi_n, + ddr4_dq => ddr4_dq, + ddr4_dqs_c => ddr4_dqs_c, + ddr4_dqs_t => ddr4_dqs_t, + mc_BG => mc_BG + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file phy_rdimm_x8_dual.vhd when simulating +-- the core, phy_rdimm_x8_dual. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U200/U200.ip_user_files/ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual_stub.v b/projects/U200/U200.ip_user_files/ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual_stub.v new file mode 100644 index 0000000..224a6a3 --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual_stub.v @@ -0,0 +1,77 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Tue Mar 8 14:28:11 2022 +// Host : machine running 64-bit Ubuntu 20.04.4 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual_stub.v +// Design : phy_rdimm_x8_dual +// Purpose : Stub declaration of top-level module interface +// Device : xcu200-fsgd2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "ddr4_v2_2_10,Vivado 2020.2" *) +module phy_rdimm_x8_dual(sys_rst, c0_sys_clk_p, c0_sys_clk_n, + c0_ddr4_ui_clk, c0_ddr4_ui_clk_sync_rst, dbg_clk, c0_ddr4_act_n, c0_ddr4_adr, c0_ddr4_ba, + c0_ddr4_bg, c0_ddr4_cke, c0_ddr4_odt, c0_ddr4_cs_n, c0_ddr4_ck_t, c0_ddr4_ck_c, + c0_ddr4_reset_n, c0_ddr4_parity, c0_ddr4_dm_dbi_n, c0_ddr4_dq, c0_ddr4_dqs_c, + c0_ddr4_dqs_t, c0_init_calib_complete, dBufAdr, wrData, wrDataMask, rdData, rdDataAddr, + rdDataEn, rdDataEnd, per_rd_done, rmw_rd_done, wrDataAddr, wrDataEn, mc_ACT_n, mc_ADR, mc_BA, + mc_BG, mc_CKE, mc_CS_n, mc_ODT, mcCasSlot, mcCasSlot2, mcRdCAS, mcWrCAS, winInjTxn, winRmw, + gt_data_ready, winBuf, winRank, tCWL, dbg_bus) +/* synthesis syn_black_box black_box_pad_pin="sys_rst,c0_sys_clk_p,c0_sys_clk_n,c0_ddr4_ui_clk,c0_ddr4_ui_clk_sync_rst,dbg_clk,c0_ddr4_act_n,c0_ddr4_adr[16:0],c0_ddr4_ba[1:0],c0_ddr4_bg[1:0],c0_ddr4_cke[0:0],c0_ddr4_odt[0:0],c0_ddr4_cs_n[0:0],c0_ddr4_ck_t[0:0],c0_ddr4_ck_c[0:0],c0_ddr4_reset_n,c0_ddr4_parity,c0_ddr4_dm_dbi_n[8:0],c0_ddr4_dq[71:0],c0_ddr4_dqs_c[8:0],c0_ddr4_dqs_t[8:0],c0_init_calib_complete,dBufAdr[4:0],wrData[575:0],wrDataMask[71:0],rdData[575:0],rdDataAddr[4:0],rdDataEn[0:0],rdDataEnd[0:0],per_rd_done[0:0],rmw_rd_done[0:0],wrDataAddr[4:0],wrDataEn[0:0],mc_ACT_n[7:0],mc_ADR[135:0],mc_BA[15:0],mc_BG[15:0],mc_CKE[7:0],mc_CS_n[7:0],mc_ODT[7:0],mcCasSlot[1:0],mcCasSlot2[0:0],mcRdCAS[0:0],mcWrCAS[0:0],winInjTxn[0:0],winRmw[0:0],gt_data_ready,winBuf[4:0],winRank[1:0],tCWL[5:0],dbg_bus[511:0]" */; + input sys_rst; + input c0_sys_clk_p; + input c0_sys_clk_n; + output c0_ddr4_ui_clk; + output c0_ddr4_ui_clk_sync_rst; + output dbg_clk; + output c0_ddr4_act_n; + output [16:0]c0_ddr4_adr; + output [1:0]c0_ddr4_ba; + output [1:0]c0_ddr4_bg; + output [0:0]c0_ddr4_cke; + output [0:0]c0_ddr4_odt; + output [0:0]c0_ddr4_cs_n; + output [0:0]c0_ddr4_ck_t; + output [0:0]c0_ddr4_ck_c; + output c0_ddr4_reset_n; + output c0_ddr4_parity; + inout [8:0]c0_ddr4_dm_dbi_n; + inout [71:0]c0_ddr4_dq; + inout [8:0]c0_ddr4_dqs_c; + inout [8:0]c0_ddr4_dqs_t; + output c0_init_calib_complete; + input [4:0]dBufAdr; + input [575:0]wrData; + input [71:0]wrDataMask; + output [575:0]rdData; + output [4:0]rdDataAddr; + output [0:0]rdDataEn; + output [0:0]rdDataEnd; + output [0:0]per_rd_done; + output [0:0]rmw_rd_done; + output [4:0]wrDataAddr; + output [0:0]wrDataEn; + input [7:0]mc_ACT_n; + input [135:0]mc_ADR; + input [15:0]mc_BA; + input [15:0]mc_BG; + input [7:0]mc_CKE; + input [7:0]mc_CS_n; + input [7:0]mc_ODT; + input [1:0]mcCasSlot; + input [0:0]mcCasSlot2; + input [0:0]mcRdCAS; + input [0:0]mcWrCAS; + input [0:0]winInjTxn; + input [0:0]winRmw; + input gt_data_ready; + input [4:0]winBuf; + input [1:0]winRank; + output [5:0]tCWL; + output [511:0]dbg_bus; +endmodule diff --git a/projects/U200/U200.ip_user_files/ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual_stub.vhdl b/projects/U200/U200.ip_user_files/ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual_stub.vhdl new file mode 100644 index 0000000..cfc2b35 --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual_stub.vhdl @@ -0,0 +1,80 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Tue Mar 8 14:28:12 2022 +-- Host : machine running 64-bit Ubuntu 20.04.4 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual_stub.vhdl +-- Design : phy_rdimm_x8_dual +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu200-fsgd2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity phy_rdimm_x8_dual is + Port ( + sys_rst : in STD_LOGIC; + c0_sys_clk_p : in STD_LOGIC; + c0_sys_clk_n : in STD_LOGIC; + c0_ddr4_ui_clk : out STD_LOGIC; + c0_ddr4_ui_clk_sync_rst : out STD_LOGIC; + dbg_clk : out STD_LOGIC; + c0_ddr4_act_n : out STD_LOGIC; + c0_ddr4_adr : out STD_LOGIC_VECTOR ( 16 downto 0 ); + c0_ddr4_ba : out STD_LOGIC_VECTOR ( 1 downto 0 ); + c0_ddr4_bg : out STD_LOGIC_VECTOR ( 1 downto 0 ); + c0_ddr4_cke : out STD_LOGIC_VECTOR ( 0 to 0 ); + c0_ddr4_odt : out STD_LOGIC_VECTOR ( 0 to 0 ); + c0_ddr4_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 ); + c0_ddr4_ck_t : out STD_LOGIC_VECTOR ( 0 to 0 ); + c0_ddr4_ck_c : out STD_LOGIC_VECTOR ( 0 to 0 ); + c0_ddr4_reset_n : out STD_LOGIC; + c0_ddr4_parity : out STD_LOGIC; + c0_ddr4_dm_dbi_n : inout STD_LOGIC_VECTOR ( 8 downto 0 ); + c0_ddr4_dq : inout STD_LOGIC_VECTOR ( 71 downto 0 ); + c0_ddr4_dqs_c : inout STD_LOGIC_VECTOR ( 8 downto 0 ); + c0_ddr4_dqs_t : inout STD_LOGIC_VECTOR ( 8 downto 0 ); + c0_init_calib_complete : out STD_LOGIC; + dBufAdr : in STD_LOGIC_VECTOR ( 4 downto 0 ); + wrData : in STD_LOGIC_VECTOR ( 575 downto 0 ); + wrDataMask : in STD_LOGIC_VECTOR ( 71 downto 0 ); + rdData : out STD_LOGIC_VECTOR ( 575 downto 0 ); + rdDataAddr : out STD_LOGIC_VECTOR ( 4 downto 0 ); + rdDataEn : out STD_LOGIC_VECTOR ( 0 to 0 ); + rdDataEnd : out STD_LOGIC_VECTOR ( 0 to 0 ); + per_rd_done : out STD_LOGIC_VECTOR ( 0 to 0 ); + rmw_rd_done : out STD_LOGIC_VECTOR ( 0 to 0 ); + wrDataAddr : out STD_LOGIC_VECTOR ( 4 downto 0 ); + wrDataEn : out STD_LOGIC_VECTOR ( 0 to 0 ); + mc_ACT_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); + mc_ADR : in STD_LOGIC_VECTOR ( 135 downto 0 ); + mc_BA : in STD_LOGIC_VECTOR ( 15 downto 0 ); + mc_BG : in STD_LOGIC_VECTOR ( 15 downto 0 ); + mc_CKE : in STD_LOGIC_VECTOR ( 7 downto 0 ); + mc_CS_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); + mc_ODT : in STD_LOGIC_VECTOR ( 7 downto 0 ); + mcCasSlot : in STD_LOGIC_VECTOR ( 1 downto 0 ); + mcCasSlot2 : in STD_LOGIC_VECTOR ( 0 to 0 ); + mcRdCAS : in STD_LOGIC_VECTOR ( 0 to 0 ); + mcWrCAS : in STD_LOGIC_VECTOR ( 0 to 0 ); + winInjTxn : in STD_LOGIC_VECTOR ( 0 to 0 ); + winRmw : in STD_LOGIC_VECTOR ( 0 to 0 ); + gt_data_ready : in STD_LOGIC; + winBuf : in STD_LOGIC_VECTOR ( 4 downto 0 ); + winRank : in STD_LOGIC_VECTOR ( 1 downto 0 ); + tCWL : out STD_LOGIC_VECTOR ( 5 downto 0 ); + dbg_bus : out STD_LOGIC_VECTOR ( 511 downto 0 ) + ); + +end phy_rdimm_x8_dual; + +architecture stub of phy_rdimm_x8_dual is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "sys_rst,c0_sys_clk_p,c0_sys_clk_n,c0_ddr4_ui_clk,c0_ddr4_ui_clk_sync_rst,dbg_clk,c0_ddr4_act_n,c0_ddr4_adr[16:0],c0_ddr4_ba[1:0],c0_ddr4_bg[1:0],c0_ddr4_cke[0:0],c0_ddr4_odt[0:0],c0_ddr4_cs_n[0:0],c0_ddr4_ck_t[0:0],c0_ddr4_ck_c[0:0],c0_ddr4_reset_n,c0_ddr4_parity,c0_ddr4_dm_dbi_n[8:0],c0_ddr4_dq[71:0],c0_ddr4_dqs_c[8:0],c0_ddr4_dqs_t[8:0],c0_init_calib_complete,dBufAdr[4:0],wrData[575:0],wrDataMask[71:0],rdData[575:0],rdDataAddr[4:0],rdDataEn[0:0],rdDataEnd[0:0],per_rd_done[0:0],rmw_rd_done[0:0],wrDataAddr[4:0],wrDataEn[0:0],mc_ACT_n[7:0],mc_ADR[135:0],mc_BA[15:0],mc_BG[15:0],mc_CKE[7:0],mc_CS_n[7:0],mc_ODT[7:0],mcCasSlot[1:0],mcCasSlot2[0:0],mcRdCAS[0:0],mcWrCAS[0:0],winInjTxn[0:0],winRmw[0:0],gt_data_ready,winBuf[4:0],winRank[1:0],tCWL[5:0],dbg_bus[511:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "ddr4_v2_2_10,Vivado 2020.2"; +begin +end; diff --git a/projects/U200/U200.ip_user_files/ip/pr_read_mem/pr_read_mem.veo b/projects/U200/U200.ip_user_files/ip/pr_read_mem/pr_read_mem.veo new file mode 100755 index 0000000..ed7e7bf --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/pr_read_mem/pr_read_mem.veo @@ -0,0 +1,70 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +// IP Revision: 4 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +pr_read_mem your_instance_name ( + .clka(clka), // input wire clka + .ena(ena), // input wire ena + .wea(wea), // input wire [0 : 0] wea + .addra(addra), // input wire [3 : 0] addra + .dina(dina), // input wire [63 : 0] dina + .douta(douta) // output wire [63 : 0] douta +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file pr_read_mem.v when simulating +// the core, pr_read_mem. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U200/U200.ip_user_files/ip/pr_read_mem/pr_read_mem.vho b/projects/U200/U200.ip_user_files/ip/pr_read_mem/pr_read_mem.vho new file mode 100755 index 0000000..26d3686 --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/pr_read_mem/pr_read_mem.vho @@ -0,0 +1,85 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +-- IP Revision: 4 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT pr_read_mem + PORT ( + clka : IN STD_LOGIC; + ena : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : pr_read_mem + PORT MAP ( + clka => clka, + ena => ena, + wea => wea, + addra => addra, + dina => dina, + douta => douta + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file pr_read_mem.vhd when simulating +-- the core, pr_read_mem. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U200/U200.ip_user_files/ip/pr_read_mem/pr_read_mem_stub.v b/projects/U200/U200.ip_user_files/ip/pr_read_mem/pr_read_mem_stub.v new file mode 100644 index 0000000..3121946 --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/pr_read_mem/pr_read_mem_stub.v @@ -0,0 +1,25 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Tue Mar 8 14:26:29 2022 +// Host : machine running 64-bit Ubuntu 20.04.4 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/pr_read_mem/pr_read_mem_stub.v +// Design : pr_read_mem +// Purpose : Stub declaration of top-level module interface +// Device : xcu200-fsgd2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2020.2" *) +module pr_read_mem(clka, ena, wea, addra, dina, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[3:0],dina[63:0],douta[63:0]" */; + input clka; + input ena; + input [0:0]wea; + input [3:0]addra; + input [63:0]dina; + output [63:0]douta; +endmodule diff --git a/projects/U200/U200.ip_user_files/ip/pr_read_mem/pr_read_mem_stub.vhdl b/projects/U200/U200.ip_user_files/ip/pr_read_mem/pr_read_mem_stub.vhdl new file mode 100644 index 0000000..2e73c55 --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/pr_read_mem/pr_read_mem_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Tue Mar 8 14:26:29 2022 +-- Host : machine running 64-bit Ubuntu 20.04.4 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/pr_read_mem/pr_read_mem_stub.vhdl +-- Design : pr_read_mem +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu200-fsgd2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity pr_read_mem is + Port ( + clka : in STD_LOGIC; + ena : in STD_LOGIC; + wea : in STD_LOGIC_VECTOR ( 0 to 0 ); + addra : in STD_LOGIC_VECTOR ( 3 downto 0 ); + dina : in STD_LOGIC_VECTOR ( 63 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 63 downto 0 ) + ); + +end pr_read_mem; + +architecture stub of pr_read_mem is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[3:0],dina[63:0],douta[63:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2020.2"; +begin +end; diff --git a/projects/U200/U200.ip_user_files/ip/pr_ref_mem/pr_ref_mem.veo b/projects/U200/U200.ip_user_files/ip/pr_ref_mem/pr_ref_mem.veo new file mode 100755 index 0000000..f8828d2 --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/pr_ref_mem/pr_ref_mem.veo @@ -0,0 +1,70 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +// IP Revision: 4 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +pr_ref_mem your_instance_name ( + .clka(clka), // input wire clka + .ena(ena), // input wire ena + .wea(wea), // input wire [0 : 0] wea + .addra(addra), // input wire [5 : 0] addra + .dina(dina), // input wire [63 : 0] dina + .douta(douta) // output wire [63 : 0] douta +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file pr_ref_mem.v when simulating +// the core, pr_ref_mem. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U200/U200.ip_user_files/ip/pr_ref_mem/pr_ref_mem.vho b/projects/U200/U200.ip_user_files/ip/pr_ref_mem/pr_ref_mem.vho new file mode 100755 index 0000000..f319d1e --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/pr_ref_mem/pr_ref_mem.vho @@ -0,0 +1,85 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +-- IP Revision: 4 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT pr_ref_mem + PORT ( + clka : IN STD_LOGIC; + ena : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : pr_ref_mem + PORT MAP ( + clka => clka, + ena => ena, + wea => wea, + addra => addra, + dina => dina, + douta => douta + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file pr_ref_mem.vhd when simulating +-- the core, pr_ref_mem. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U200/U200.ip_user_files/ip/pr_ref_mem/pr_ref_mem_stub.v b/projects/U200/U200.ip_user_files/ip/pr_ref_mem/pr_ref_mem_stub.v new file mode 100644 index 0000000..277b54f --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/pr_ref_mem/pr_ref_mem_stub.v @@ -0,0 +1,25 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Tue Mar 8 14:26:58 2022 +// Host : machine running 64-bit Ubuntu 20.04.4 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem_stub.v +// Design : pr_ref_mem +// Purpose : Stub declaration of top-level module interface +// Device : xcu200-fsgd2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2020.2" *) +module pr_ref_mem(clka, ena, wea, addra, dina, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[5:0],dina[63:0],douta[63:0]" */; + input clka; + input ena; + input [0:0]wea; + input [5:0]addra; + input [63:0]dina; + output [63:0]douta; +endmodule diff --git a/projects/U200/U200.ip_user_files/ip/pr_ref_mem/pr_ref_mem_stub.vhdl b/projects/U200/U200.ip_user_files/ip/pr_ref_mem/pr_ref_mem_stub.vhdl new file mode 100644 index 0000000..0709d2a --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/pr_ref_mem/pr_ref_mem_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Tue Mar 8 14:26:58 2022 +-- Host : machine running 64-bit Ubuntu 20.04.4 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem_stub.vhdl +-- Design : pr_ref_mem +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu200-fsgd2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity pr_ref_mem is + Port ( + clka : in STD_LOGIC; + ena : in STD_LOGIC; + wea : in STD_LOGIC_VECTOR ( 0 to 0 ); + addra : in STD_LOGIC_VECTOR ( 5 downto 0 ); + dina : in STD_LOGIC_VECTOR ( 63 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 63 downto 0 ) + ); + +end pr_ref_mem; + +architecture stub of pr_ref_mem is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[5:0],dina[63:0],douta[63:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2020.2"; +begin +end; diff --git a/projects/U200/U200.ip_user_files/ip/rdback_fifo/rdback_fifo.veo b/projects/U200/U200.ip_user_files/ip/rdback_fifo/rdback_fifo.veo new file mode 100755 index 0000000..f460ca0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/rdback_fifo/rdback_fifo.veo @@ -0,0 +1,77 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:fifo_generator:13.2 +// IP Revision: 5 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +rdback_fifo your_instance_name ( + .clk(clk), // input wire clk + .srst(srst), // input wire srst + .din(din), // input wire [511 : 0] din + .wr_en(wr_en), // input wire wr_en + .rd_en(rd_en), // input wire rd_en + .dout(dout), // output wire [255 : 0] dout + .full(full), // output wire full + .empty(empty), // output wire empty + .valid(valid), // output wire valid + .prog_full(prog_full), // output wire prog_full + .prog_empty(prog_empty), // output wire prog_empty + .wr_rst_busy(wr_rst_busy), // output wire wr_rst_busy + .rd_rst_busy(rd_rst_busy) // output wire rd_rst_busy +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file rdback_fifo.v when simulating +// the core, rdback_fifo. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U200/U200.ip_user_files/ip/rdback_fifo/rdback_fifo.vho b/projects/U200/U200.ip_user_files/ip/rdback_fifo/rdback_fifo.vho new file mode 100755 index 0000000..b2312a7 --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/rdback_fifo/rdback_fifo.vho @@ -0,0 +1,99 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:fifo_generator:13.2 +-- IP Revision: 5 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT rdback_fifo + PORT ( + clk : IN STD_LOGIC; + srst : IN STD_LOGIC; + din : IN STD_LOGIC_VECTOR(511 DOWNTO 0); + wr_en : IN STD_LOGIC; + rd_en : IN STD_LOGIC; + dout : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + full : OUT STD_LOGIC; + empty : OUT STD_LOGIC; + valid : OUT STD_LOGIC; + prog_full : OUT STD_LOGIC; + prog_empty : OUT STD_LOGIC; + wr_rst_busy : OUT STD_LOGIC; + rd_rst_busy : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : rdback_fifo + PORT MAP ( + clk => clk, + srst => srst, + din => din, + wr_en => wr_en, + rd_en => rd_en, + dout => dout, + full => full, + empty => empty, + valid => valid, + prog_full => prog_full, + prog_empty => prog_empty, + wr_rst_busy => wr_rst_busy, + rd_rst_busy => rd_rst_busy + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file rdback_fifo.vhd when simulating +-- the core, rdback_fifo. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U200/U200.ip_user_files/ip/rdback_fifo/rdback_fifo_stub.v b/projects/U200/U200.ip_user_files/ip/rdback_fifo/rdback_fifo_stub.v new file mode 100644 index 0000000..2467ff2 --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/rdback_fifo/rdback_fifo_stub.v @@ -0,0 +1,33 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Tue Mar 8 14:26:56 2022 +// Host : machine running 64-bit Ubuntu 20.04.4 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/rdback_fifo/rdback_fifo_stub.v +// Design : rdback_fifo +// Purpose : Stub declaration of top-level module interface +// Device : xcu200-fsgd2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "fifo_generator_v13_2_5,Vivado 2020.2" *) +module rdback_fifo(clk, srst, din, wr_en, rd_en, dout, full, empty, valid, + prog_full, prog_empty, wr_rst_busy, rd_rst_busy) +/* synthesis syn_black_box black_box_pad_pin="clk,srst,din[511:0],wr_en,rd_en,dout[255:0],full,empty,valid,prog_full,prog_empty,wr_rst_busy,rd_rst_busy" */; + input clk; + input srst; + input [511:0]din; + input wr_en; + input rd_en; + output [255:0]dout; + output full; + output empty; + output valid; + output prog_full; + output prog_empty; + output wr_rst_busy; + output rd_rst_busy; +endmodule diff --git a/projects/U200/U200.ip_user_files/ip/rdback_fifo/rdback_fifo_stub.vhdl b/projects/U200/U200.ip_user_files/ip/rdback_fifo/rdback_fifo_stub.vhdl new file mode 100644 index 0000000..b6ee5dd --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/rdback_fifo/rdback_fifo_stub.vhdl @@ -0,0 +1,42 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Tue Mar 8 14:26:56 2022 +-- Host : machine running 64-bit Ubuntu 20.04.4 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/rdback_fifo/rdback_fifo_stub.vhdl +-- Design : rdback_fifo +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu200-fsgd2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity rdback_fifo is + Port ( + clk : in STD_LOGIC; + srst : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 511 downto 0 ); + wr_en : in STD_LOGIC; + rd_en : in STD_LOGIC; + dout : out STD_LOGIC_VECTOR ( 255 downto 0 ); + full : out STD_LOGIC; + empty : out STD_LOGIC; + valid : out STD_LOGIC; + prog_full : out STD_LOGIC; + prog_empty : out STD_LOGIC; + wr_rst_busy : out STD_LOGIC; + rd_rst_busy : out STD_LOGIC + ); + +end rdback_fifo; + +architecture stub of rdback_fifo is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,srst,din[511:0],wr_en,rd_en,dout[255:0],full,empty,valid,prog_full,prog_empty,wr_rst_busy,rd_rst_busy"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "fifo_generator_v13_2_5,Vivado 2020.2"; +begin +end; diff --git a/projects/U200/U200.ip_user_files/ip/scratchpad/scratchpad.veo b/projects/U200/U200.ip_user_files/ip/scratchpad/scratchpad.veo new file mode 100755 index 0000000..94ad2db --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/scratchpad/scratchpad.veo @@ -0,0 +1,70 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +// IP Revision: 4 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +scratchpad your_instance_name ( + .clka(clka), // input wire clka + .ena(ena), // input wire ena + .wea(wea), // input wire [0 : 0] wea + .addra(addra), // input wire [9 : 0] addra + .dina(dina), // input wire [31 : 0] dina + .douta(douta) // output wire [31 : 0] douta +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file scratchpad.v when simulating +// the core, scratchpad. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U200/U200.ip_user_files/ip/scratchpad/scratchpad.vho b/projects/U200/U200.ip_user_files/ip/scratchpad/scratchpad.vho new file mode 100755 index 0000000..9f4ca48 --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/scratchpad/scratchpad.vho @@ -0,0 +1,85 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +-- IP Revision: 4 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT scratchpad + PORT ( + clka : IN STD_LOGIC; + ena : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : scratchpad + PORT MAP ( + clka => clka, + ena => ena, + wea => wea, + addra => addra, + dina => dina, + douta => douta + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file scratchpad.vhd when simulating +-- the core, scratchpad. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U200/U200.ip_user_files/ip/scratchpad/scratchpad_stub.v b/projects/U200/U200.ip_user_files/ip/scratchpad/scratchpad_stub.v new file mode 100644 index 0000000..9db516d --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/scratchpad/scratchpad_stub.v @@ -0,0 +1,25 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Tue Mar 8 14:28:30 2022 +// Host : machine running 64-bit Ubuntu 20.04.4 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/scratchpad/scratchpad_stub.v +// Design : scratchpad +// Purpose : Stub declaration of top-level module interface +// Device : xcu200-fsgd2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2020.2" *) +module scratchpad(clka, ena, wea, addra, dina, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[9:0],dina[31:0],douta[31:0]" */; + input clka; + input ena; + input [0:0]wea; + input [9:0]addra; + input [31:0]dina; + output [31:0]douta; +endmodule diff --git a/projects/U200/U200.ip_user_files/ip/scratchpad/scratchpad_stub.vhdl b/projects/U200/U200.ip_user_files/ip/scratchpad/scratchpad_stub.vhdl new file mode 100644 index 0000000..5714675 --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/scratchpad/scratchpad_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Tue Mar 8 14:28:30 2022 +-- Host : machine running 64-bit Ubuntu 20.04.4 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/scratchpad/scratchpad_stub.vhdl +-- Design : scratchpad +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu200-fsgd2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity scratchpad is + Port ( + clka : in STD_LOGIC; + ena : in STD_LOGIC; + wea : in STD_LOGIC_VECTOR ( 0 to 0 ); + addra : in STD_LOGIC_VECTOR ( 9 downto 0 ); + dina : in STD_LOGIC_VECTOR ( 31 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + +end scratchpad; + +architecture stub of scratchpad is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[9:0],dina[31:0],douta[31:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2020.2"; +begin +end; diff --git a/projects/U200/U200.ip_user_files/ip/xdma/xdma.veo b/projects/U200/U200.ip_user_files/ip/xdma/xdma.veo new file mode 100755 index 0000000..3ea245b --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/xdma/xdma.veo @@ -0,0 +1,95 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:xdma:4.1 +// IP Revision: 8 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +xdma your_instance_name ( + .sys_clk(sys_clk), // input wire sys_clk + .sys_clk_gt(sys_clk_gt), // input wire sys_clk_gt + .sys_rst_n(sys_rst_n), // input wire sys_rst_n + .user_lnk_up(user_lnk_up), // output wire user_lnk_up + .pci_exp_txp(pci_exp_txp), // output wire [7 : 0] pci_exp_txp + .pci_exp_txn(pci_exp_txn), // output wire [7 : 0] pci_exp_txn + .pci_exp_rxp(pci_exp_rxp), // input wire [7 : 0] pci_exp_rxp + .pci_exp_rxn(pci_exp_rxn), // input wire [7 : 0] pci_exp_rxn + .axi_aclk(axi_aclk), // output wire axi_aclk + .axi_aresetn(axi_aresetn), // output wire axi_aresetn + .usr_irq_req(usr_irq_req), // input wire [0 : 0] usr_irq_req + .usr_irq_ack(usr_irq_ack), // output wire [0 : 0] usr_irq_ack + .msi_enable(msi_enable), // output wire msi_enable + .msi_vector_width(msi_vector_width), // output wire [2 : 0] msi_vector_width + .cfg_mgmt_addr(cfg_mgmt_addr), // input wire [18 : 0] cfg_mgmt_addr + .cfg_mgmt_write(cfg_mgmt_write), // input wire cfg_mgmt_write + .cfg_mgmt_write_data(cfg_mgmt_write_data), // input wire [31 : 0] cfg_mgmt_write_data + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), // input wire [3 : 0] cfg_mgmt_byte_enable + .cfg_mgmt_read(cfg_mgmt_read), // input wire cfg_mgmt_read + .cfg_mgmt_read_data(cfg_mgmt_read_data), // output wire [31 : 0] cfg_mgmt_read_data + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), // output wire cfg_mgmt_read_write_done + .s_axis_c2h_tdata_0(s_axis_c2h_tdata_0), // input wire [255 : 0] s_axis_c2h_tdata_0 + .s_axis_c2h_tlast_0(s_axis_c2h_tlast_0), // input wire s_axis_c2h_tlast_0 + .s_axis_c2h_tvalid_0(s_axis_c2h_tvalid_0), // input wire s_axis_c2h_tvalid_0 + .s_axis_c2h_tready_0(s_axis_c2h_tready_0), // output wire s_axis_c2h_tready_0 + .s_axis_c2h_tkeep_0(s_axis_c2h_tkeep_0), // input wire [31 : 0] s_axis_c2h_tkeep_0 + .m_axis_h2c_tdata_0(m_axis_h2c_tdata_0), // output wire [255 : 0] m_axis_h2c_tdata_0 + .m_axis_h2c_tlast_0(m_axis_h2c_tlast_0), // output wire m_axis_h2c_tlast_0 + .m_axis_h2c_tvalid_0(m_axis_h2c_tvalid_0), // output wire m_axis_h2c_tvalid_0 + .m_axis_h2c_tready_0(m_axis_h2c_tready_0), // input wire m_axis_h2c_tready_0 + .m_axis_h2c_tkeep_0(m_axis_h2c_tkeep_0) // output wire [31 : 0] m_axis_h2c_tkeep_0 +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file xdma.v when simulating +// the core, xdma. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U200/U200.ip_user_files/ip/xdma/xdma.vho b/projects/U200/U200.ip_user_files/ip/xdma/xdma.vho new file mode 100755 index 0000000..35829f6 --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/xdma/xdma.vho @@ -0,0 +1,135 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:xdma:4.1 +-- IP Revision: 8 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT xdma + PORT ( + sys_clk : IN STD_LOGIC; + sys_clk_gt : IN STD_LOGIC; + sys_rst_n : IN STD_LOGIC; + user_lnk_up : OUT STD_LOGIC; + pci_exp_txp : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + pci_exp_txn : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + pci_exp_rxp : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + pci_exp_rxn : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + axi_aclk : OUT STD_LOGIC; + axi_aresetn : OUT STD_LOGIC; + usr_irq_req : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + usr_irq_ack : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + msi_enable : OUT STD_LOGIC; + msi_vector_width : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + cfg_mgmt_addr : IN STD_LOGIC_VECTOR(18 DOWNTO 0); + cfg_mgmt_write : IN STD_LOGIC; + cfg_mgmt_write_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + cfg_mgmt_byte_enable : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + cfg_mgmt_read : IN STD_LOGIC; + cfg_mgmt_read_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + cfg_mgmt_read_write_done : OUT STD_LOGIC; + s_axis_c2h_tdata_0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + s_axis_c2h_tlast_0 : IN STD_LOGIC; + s_axis_c2h_tvalid_0 : IN STD_LOGIC; + s_axis_c2h_tready_0 : OUT STD_LOGIC; + s_axis_c2h_tkeep_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axis_h2c_tdata_0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + m_axis_h2c_tlast_0 : OUT STD_LOGIC; + m_axis_h2c_tvalid_0 : OUT STD_LOGIC; + m_axis_h2c_tready_0 : IN STD_LOGIC; + m_axis_h2c_tkeep_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : xdma + PORT MAP ( + sys_clk => sys_clk, + sys_clk_gt => sys_clk_gt, + sys_rst_n => sys_rst_n, + user_lnk_up => user_lnk_up, + pci_exp_txp => pci_exp_txp, + pci_exp_txn => pci_exp_txn, + pci_exp_rxp => pci_exp_rxp, + pci_exp_rxn => pci_exp_rxn, + axi_aclk => axi_aclk, + axi_aresetn => axi_aresetn, + usr_irq_req => usr_irq_req, + usr_irq_ack => usr_irq_ack, + msi_enable => msi_enable, + msi_vector_width => msi_vector_width, + cfg_mgmt_addr => cfg_mgmt_addr, + cfg_mgmt_write => cfg_mgmt_write, + cfg_mgmt_write_data => cfg_mgmt_write_data, + cfg_mgmt_byte_enable => cfg_mgmt_byte_enable, + cfg_mgmt_read => cfg_mgmt_read, + cfg_mgmt_read_data => cfg_mgmt_read_data, + cfg_mgmt_read_write_done => cfg_mgmt_read_write_done, + s_axis_c2h_tdata_0 => s_axis_c2h_tdata_0, + s_axis_c2h_tlast_0 => s_axis_c2h_tlast_0, + s_axis_c2h_tvalid_0 => s_axis_c2h_tvalid_0, + s_axis_c2h_tready_0 => s_axis_c2h_tready_0, + s_axis_c2h_tkeep_0 => s_axis_c2h_tkeep_0, + m_axis_h2c_tdata_0 => m_axis_h2c_tdata_0, + m_axis_h2c_tlast_0 => m_axis_h2c_tlast_0, + m_axis_h2c_tvalid_0 => m_axis_h2c_tvalid_0, + m_axis_h2c_tready_0 => m_axis_h2c_tready_0, + m_axis_h2c_tkeep_0 => m_axis_h2c_tkeep_0 + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file xdma.vhd when simulating +-- the core, xdma. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U200/U200.ip_user_files/ip/xdma/xdma_stub.v b/projects/U200/U200.ip_user_files/ip/xdma/xdma_stub.v new file mode 100644 index 0000000..2267a77 --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/xdma/xdma_stub.v @@ -0,0 +1,56 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Tue Mar 8 14:33:03 2022 +// Host : machine running 64-bit Ubuntu 20.04.4 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/xdma/xdma_stub.v +// Design : xdma +// Purpose : Stub declaration of top-level module interface +// Device : xcu200-fsgd2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "xdma_core_top,Vivado 2020.2" *) +module xdma(sys_clk, sys_clk_gt, sys_rst_n, user_lnk_up, + pci_exp_txp, pci_exp_txn, pci_exp_rxp, pci_exp_rxn, axi_aclk, axi_aresetn, usr_irq_req, + usr_irq_ack, msi_enable, msi_vector_width, cfg_mgmt_addr, cfg_mgmt_write, + cfg_mgmt_write_data, cfg_mgmt_byte_enable, cfg_mgmt_read, cfg_mgmt_read_data, + cfg_mgmt_read_write_done, s_axis_c2h_tdata_0, s_axis_c2h_tlast_0, s_axis_c2h_tvalid_0, + s_axis_c2h_tready_0, s_axis_c2h_tkeep_0, m_axis_h2c_tdata_0, m_axis_h2c_tlast_0, + m_axis_h2c_tvalid_0, m_axis_h2c_tready_0, m_axis_h2c_tkeep_0) +/* synthesis syn_black_box black_box_pad_pin="sys_clk,sys_clk_gt,sys_rst_n,user_lnk_up,pci_exp_txp[7:0],pci_exp_txn[7:0],pci_exp_rxp[7:0],pci_exp_rxn[7:0],axi_aclk,axi_aresetn,usr_irq_req[0:0],usr_irq_ack[0:0],msi_enable,msi_vector_width[2:0],cfg_mgmt_addr[18:0],cfg_mgmt_write,cfg_mgmt_write_data[31:0],cfg_mgmt_byte_enable[3:0],cfg_mgmt_read,cfg_mgmt_read_data[31:0],cfg_mgmt_read_write_done,s_axis_c2h_tdata_0[255:0],s_axis_c2h_tlast_0,s_axis_c2h_tvalid_0,s_axis_c2h_tready_0,s_axis_c2h_tkeep_0[31:0],m_axis_h2c_tdata_0[255:0],m_axis_h2c_tlast_0,m_axis_h2c_tvalid_0,m_axis_h2c_tready_0,m_axis_h2c_tkeep_0[31:0]" */; + input sys_clk; + input sys_clk_gt; + input sys_rst_n; + output user_lnk_up; + output [7:0]pci_exp_txp; + output [7:0]pci_exp_txn; + input [7:0]pci_exp_rxp; + input [7:0]pci_exp_rxn; + output axi_aclk; + output axi_aresetn; + input [0:0]usr_irq_req; + output [0:0]usr_irq_ack; + output msi_enable; + output [2:0]msi_vector_width; + input [18:0]cfg_mgmt_addr; + input cfg_mgmt_write; + input [31:0]cfg_mgmt_write_data; + input [3:0]cfg_mgmt_byte_enable; + input cfg_mgmt_read; + output [31:0]cfg_mgmt_read_data; + output cfg_mgmt_read_write_done; + input [255:0]s_axis_c2h_tdata_0; + input s_axis_c2h_tlast_0; + input s_axis_c2h_tvalid_0; + output s_axis_c2h_tready_0; + input [31:0]s_axis_c2h_tkeep_0; + output [255:0]m_axis_h2c_tdata_0; + output m_axis_h2c_tlast_0; + output m_axis_h2c_tvalid_0; + input m_axis_h2c_tready_0; + output [31:0]m_axis_h2c_tkeep_0; +endmodule diff --git a/projects/U200/U200.ip_user_files/ip/xdma/xdma_stub.vhdl b/projects/U200/U200.ip_user_files/ip/xdma/xdma_stub.vhdl new file mode 100644 index 0000000..45c3cdc --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/xdma/xdma_stub.vhdl @@ -0,0 +1,60 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Tue Mar 8 14:33:04 2022 +-- Host : machine running 64-bit Ubuntu 20.04.4 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/xdma/xdma_stub.vhdl +-- Design : xdma +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu200-fsgd2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity xdma is + Port ( + sys_clk : in STD_LOGIC; + sys_clk_gt : in STD_LOGIC; + sys_rst_n : in STD_LOGIC; + user_lnk_up : out STD_LOGIC; + pci_exp_txp : out STD_LOGIC_VECTOR ( 7 downto 0 ); + pci_exp_txn : out STD_LOGIC_VECTOR ( 7 downto 0 ); + pci_exp_rxp : in STD_LOGIC_VECTOR ( 7 downto 0 ); + pci_exp_rxn : in STD_LOGIC_VECTOR ( 7 downto 0 ); + axi_aclk : out STD_LOGIC; + axi_aresetn : out STD_LOGIC; + usr_irq_req : in STD_LOGIC_VECTOR ( 0 to 0 ); + usr_irq_ack : out STD_LOGIC_VECTOR ( 0 to 0 ); + msi_enable : out STD_LOGIC; + msi_vector_width : out STD_LOGIC_VECTOR ( 2 downto 0 ); + cfg_mgmt_addr : in STD_LOGIC_VECTOR ( 18 downto 0 ); + cfg_mgmt_write : in STD_LOGIC; + cfg_mgmt_write_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); + cfg_mgmt_byte_enable : in STD_LOGIC_VECTOR ( 3 downto 0 ); + cfg_mgmt_read : in STD_LOGIC; + cfg_mgmt_read_data : out STD_LOGIC_VECTOR ( 31 downto 0 ); + cfg_mgmt_read_write_done : out STD_LOGIC; + s_axis_c2h_tdata_0 : in STD_LOGIC_VECTOR ( 255 downto 0 ); + s_axis_c2h_tlast_0 : in STD_LOGIC; + s_axis_c2h_tvalid_0 : in STD_LOGIC; + s_axis_c2h_tready_0 : out STD_LOGIC; + s_axis_c2h_tkeep_0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axis_h2c_tdata_0 : out STD_LOGIC_VECTOR ( 255 downto 0 ); + m_axis_h2c_tlast_0 : out STD_LOGIC; + m_axis_h2c_tvalid_0 : out STD_LOGIC; + m_axis_h2c_tready_0 : in STD_LOGIC; + m_axis_h2c_tkeep_0 : out STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + +end xdma; + +architecture stub of xdma is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "sys_clk,sys_clk_gt,sys_rst_n,user_lnk_up,pci_exp_txp[7:0],pci_exp_txn[7:0],pci_exp_rxp[7:0],pci_exp_rxn[7:0],axi_aclk,axi_aresetn,usr_irq_req[0:0],usr_irq_ack[0:0],msi_enable,msi_vector_width[2:0],cfg_mgmt_addr[18:0],cfg_mgmt_write,cfg_mgmt_write_data[31:0],cfg_mgmt_byte_enable[3:0],cfg_mgmt_read,cfg_mgmt_read_data[31:0],cfg_mgmt_read_write_done,s_axis_c2h_tdata_0[255:0],s_axis_c2h_tlast_0,s_axis_c2h_tvalid_0,s_axis_c2h_tready_0,s_axis_c2h_tkeep_0[31:0],m_axis_h2c_tdata_0[255:0],m_axis_h2c_tlast_0,m_axis_h2c_tvalid_0,m_axis_h2c_tready_0,m_axis_h2c_tkeep_0[31:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "xdma_core_top,Vivado 2020.2"; +begin +end; diff --git a/projects/U200/U200.ip_user_files/ip/zq_calib_mem/zq_calib_mem.veo b/projects/U200/U200.ip_user_files/ip/zq_calib_mem/zq_calib_mem.veo new file mode 100755 index 0000000..6dac95b --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/zq_calib_mem/zq_calib_mem.veo @@ -0,0 +1,70 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +// IP Revision: 4 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +zq_calib_mem your_instance_name ( + .clka(clka), // input wire clka + .ena(ena), // input wire ena + .wea(wea), // input wire [0 : 0] wea + .addra(addra), // input wire [5 : 0] addra + .dina(dina), // input wire [63 : 0] dina + .douta(douta) // output wire [63 : 0] douta +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file zq_calib_mem.v when simulating +// the core, zq_calib_mem. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U200/U200.ip_user_files/ip/zq_calib_mem/zq_calib_mem.vho b/projects/U200/U200.ip_user_files/ip/zq_calib_mem/zq_calib_mem.vho new file mode 100755 index 0000000..2763f20 --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/zq_calib_mem/zq_calib_mem.vho @@ -0,0 +1,85 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +-- IP Revision: 4 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT zq_calib_mem + PORT ( + clka : IN STD_LOGIC; + ena : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : zq_calib_mem + PORT MAP ( + clka => clka, + ena => ena, + wea => wea, + addra => addra, + dina => dina, + douta => douta + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file zq_calib_mem.vhd when simulating +-- the core, zq_calib_mem. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U200/U200.ip_user_files/ip/zq_calib_mem/zq_calib_mem_stub.v b/projects/U200/U200.ip_user_files/ip/zq_calib_mem/zq_calib_mem_stub.v new file mode 100644 index 0000000..21c89b3 --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/zq_calib_mem/zq_calib_mem_stub.v @@ -0,0 +1,25 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Tue Mar 8 14:28:50 2022 +// Host : machine running 64-bit Ubuntu 20.04.4 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem_stub.v +// Design : zq_calib_mem +// Purpose : Stub declaration of top-level module interface +// Device : xcu200-fsgd2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2020.2" *) +module zq_calib_mem(clka, ena, wea, addra, dina, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[5:0],dina[63:0],douta[63:0]" */; + input clka; + input ena; + input [0:0]wea; + input [5:0]addra; + input [63:0]dina; + output [63:0]douta; +endmodule diff --git a/projects/U200/U200.ip_user_files/ip/zq_calib_mem/zq_calib_mem_stub.vhdl b/projects/U200/U200.ip_user_files/ip/zq_calib_mem/zq_calib_mem_stub.vhdl new file mode 100644 index 0000000..cc5c23a --- /dev/null +++ b/projects/U200/U200.ip_user_files/ip/zq_calib_mem/zq_calib_mem_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Tue Mar 8 14:28:51 2022 +-- Host : machine running 64-bit Ubuntu 20.04.4 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem_stub.vhdl +-- Design : zq_calib_mem +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu200-fsgd2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity zq_calib_mem is + Port ( + clka : in STD_LOGIC; + ena : in STD_LOGIC; + wea : in STD_LOGIC_VECTOR ( 0 to 0 ); + addra : in STD_LOGIC_VECTOR ( 5 downto 0 ); + dina : in STD_LOGIC_VECTOR ( 63 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 63 downto 0 ) + ); + +end zq_calib_mem; + +architecture stub of zq_calib_mem is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[5:0],dina[63:0],douta[63:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2020.2"; +begin +end; |